mirror of https://github.com/YosysHQ/yosys.git
fixing code style
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@ -298,7 +298,7 @@ struct EquivMakeWorker
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SigSpec new_sig = rd_signal_map(old_sig);
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if(old_sig != new_sig) {
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for(auto & old_bit : old_sig.bits()) {
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for (auto &old_bit : old_sig.bits()) {
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SigBit new_bit = new_sig.bits()[old_bit.offset];
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visited_cells.clear();
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