mirror of https://github.com/YosysHQ/yosys.git
Cleanup
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@ -671,26 +671,23 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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int in_wires = 0, out_wires = 0;
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int in_wires = 0, out_wires = 0;
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// Stitch in mapped_mod's inputs/outputs into module
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// Stitch in mapped_mod's inputs/outputs into module
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// TODO: iterate using ports
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for (auto port_name : mapped_mod->ports) {
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for (auto &it : mapped_mod->wires_) {
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RTLIL::Wire *port = mapped_mod->wire(port_name);
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RTLIL::Wire *w = it.second;
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log_assert(port);
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if (!w->port_input && !w->port_output)
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RTLIL::Wire *wire = module->wire(port->name);
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continue;
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RTLIL::Wire *wire = module->wire(w->name);
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log_assert(wire);
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log_assert(wire);
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RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
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RTLIL::Wire *remap_wire = module->wire(remap_name(port->name));
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RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
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RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
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log_assert(GetSize(signal) >= GetSize(remap_wire));
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log_assert(GetSize(signal) >= GetSize(remap_wire));
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log_assert(w->port_input || w->port_output);
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RTLIL::SigSig conn;
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RTLIL::SigSig conn;
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if (w->port_input) {
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if (port->port_input) {
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conn.first = remap_wire;
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conn.first = remap_wire;
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conn.second = signal;
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conn.second = signal;
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in_wires++;
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in_wires++;
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module->connect(conn);
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module->connect(conn);
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}
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}
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if (w->port_output) {
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if (port->port_output) {
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conn.first = signal;
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conn.first = signal;
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conn.second = remap_wire;
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conn.second = remap_wire;
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out_wires++;
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out_wires++;
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