diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 94dbf31c0..a5fbfeda4 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3438,7 +3438,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 
 	if (width_ < width) {
 		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
-		if (!is_signed)
+		if (padding != RTLIL::State::Sx && !is_signed)
 			padding = RTLIL::State::S0;
 		while (width_ < width)
 			append(padding);
diff --git a/tests/various/signext.ys b/tests/various/signext.ys
new file mode 100644
index 000000000..ae44a0e06
--- /dev/null
+++ b/tests/various/signext.ys
@@ -0,0 +1,21 @@
+
+read_verilog -formal <<EOT
+module gate(input clk, output [1:0] o);
+assign o = 1'bx;
+endmodule
+EOT
+
+proc
+
+## Equivalence checking
+
+read_verilog -formal <<EOT
+module gold(input clk, output [1:0] o);
+assign o = 2'bxx;
+endmodule
+EOT
+
+proc
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -enable_undef miter