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Add multi clock test

This commit is contained in:
Eddie Hung 2019-11-20 13:28:55 -08:00
parent df63d75ff3
commit cd9e830b67
1 changed files with 5 additions and 0 deletions
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5
tests/simple_abc9/abc9.v
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@ -267,3 +267,8 @@ module abc9_test026(output [3:0] o, p);
assign o = { 1'b1, 1'bx };
assign p = { 1'b1, 1'bx, 1'b0 };
endmodule
module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
always @(posedge clk1) q1 <= d;
always @(negedge clk2) q2 <= q1;
endmodule