mirror of https://github.com/YosysHQ/yosys.git
[wip] sim model testing
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
parent
fe95807f16
commit
ccfb4ff2a9
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@ -463,27 +463,10 @@ module DSP48E1 (
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initial begin
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initial begin
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`ifdef __ICARUS__
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`ifdef __ICARUS__
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if (ACASCREG != 0) $fatal(1, "Unsupported ACASCREG value");
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if (ADREG != 0) $fatal(1, "Unsupported ADREG value");
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if (ALUMODEREG != 0) $fatal(1, "Unsupported ALUMODEREG value");
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if (AREG == 2) $fatal(1, "Unsupported AREG value");
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if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
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if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
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if (A_INPUT != "DIRECT") $fatal(1, "Unsupported A_INPUT value");
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if (BCASCREG != 0) $fatal(1, "Unsupported BCASCREG value");
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if (BREG == 2) $fatal(1, "Unsupported BREG value");
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if (B_INPUT != "DIRECT") $fatal(1, "Unsupported B_INPUT value");
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if (CARRYINREG != 0) $fatal(1, "Unsupported CARRYINREG value");
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if (CARRYINSELREG != 0) $fatal(1, "Unsupported CARRYINSELREG value");
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if (CREG != 0) $fatal(1, "Unsupported CREG value");
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if (DREG != 0) $fatal(1, "Unsupported DREG value");
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if (INMODEREG != 0) $fatal(1, "Unsupported INMODEREG value");
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if (MREG != 0) $fatal(1, "Unsupported MREG value");
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if (OPMODEREG != 0) $fatal(1, "Unsupported OPMODEREG value");
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//if (PREG != 0) $fatal(1, "Unsupported PREG value");
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//if (PREG != 0) $fatal(1, "Unsupported PREG value");
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if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
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if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
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if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
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if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
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if (USE_DPORT != "FALSE") $fatal(1, "Unsupported USE_DPORT value");
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if (USE_MULT != "MULTIPLY") $fatal(1, "Unsupported USE_MULT value");
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if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value");
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if (USE_PATTERN_DETECT != "NO_PATDET") $fatal(1, "Unsupported USE_PATTERN_DETECT value");
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if (USE_SIMD != "ONE48") $fatal(1, "Unsupported USE_SIMD value");
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if (USE_SIMD != "ONE48") $fatal(1, "Unsupported USE_SIMD value");
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if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value");
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if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value");
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@ -505,14 +488,14 @@ module DSP48E1 (
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else assign B_muxed = B;
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else assign B_muxed = B;
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endgenerate
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endgenerate
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reg signed [29:0] Ar1, Ar2;
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reg signed [29:0] Ar1 = 30'b0, Ar2 = 30'b0;
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reg signed [24:0] Dr;
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reg signed [24:0] Dr = 25'b0;
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reg signed [17:0] Br1, Br2;
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reg signed [17:0] Br1 = 18'b0, Br2 = 18'b0;
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reg signed [47:0] Cr;
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reg signed [47:0] Cr = 48'b0;
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reg [4:0] INMODEr;
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reg [4:0] INMODEr = 5'b0;
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reg [6:0] OPMODEr;
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reg [6:0] OPMODEr = 7'b0;
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reg [3:0] ALUMODEr;
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reg [3:0] ALUMODEr = 4'b0;
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reg [2:0] CARRYINSELr;
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reg [2:0] CARRYINSELr = 3'b0;
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generate
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generate
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// Configurable A register
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// Configurable A register
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@ -594,7 +577,7 @@ module DSP48E1 (
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wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed;
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wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed;
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wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0;
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wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0;
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wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated);
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wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated);
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reg signed [24:0] ADr;
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reg signed [24:0] ADr = 25'b0;
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generate
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generate
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if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end
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if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end
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@ -610,7 +593,7 @@ module DSP48E1 (
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endgenerate
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endgenerate
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wire signed [42:0] M = A_MULT * B_MULT;
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wire signed [42:0] M = A_MULT * B_MULT;
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reg signed [42:0] Mr;
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reg signed [42:0] Mr = 43'b0;
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// Multiplier result register
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// Multiplier result register
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generate
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generate
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@ -625,14 +608,16 @@ module DSP48E1 (
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// X multiplexer
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// X multiplexer
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case (OPMODEr[1:0])
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case (OPMODEr[1:0])
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2'b00: X = 48'b0;
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2'b00: X = 48'b0;
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2'b01: X = $signed(M);
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2'b01: begin X = $signed(M);
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`ifdef __ICARUS__
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`ifdef __ICARUS__
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if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
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if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
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`endif
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`endif
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2'b10: X = P;
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end
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2'b10: begin X = P;
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`ifdef __ICARUS__
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`ifdef __ICARUS__
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
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`endif
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`endif
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end
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2'b11: X = $signed({Ar2, Br2});
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2'b11: X = $signed({Ar2, Br2});
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default: X = 48'bx;
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default: X = 48'bx;
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endcase
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endcase
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@ -640,10 +625,11 @@ module DSP48E1 (
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// Y multiplexer
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// Y multiplexer
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case (OPMODEr[3:2])
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case (OPMODEr[3:2])
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2'b00: Y = 48'b0;
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2'b00: Y = 48'b0;
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2'b01: Y = 48'b0; // FIXME: more accurate partial product modelling?
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2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling?
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`ifdef __ICARUS__
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`ifdef __ICARUS__
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if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
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if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
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`endif
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`endif
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end
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2'b10: Y = {48{1'b1}};
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2'b10: Y = {48{1'b1}};
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2'b11: Y = C;
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2'b11: Y = C;
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default: Y = 48'bx;
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default: Y = 48'bx;
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@ -653,26 +639,54 @@ module DSP48E1 (
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case (OPMODEr[6:4])
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case (OPMODEr[6:4])
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3'b000: Z = 48'b0;
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3'b000: Z = 48'b0;
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3'b001: Z = PCIN;
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3'b001: Z = PCIN;
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3'b010: Z = P;
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3'b010: begin Z = P;
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`ifdef __ICARUS__
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`ifdef __ICARUS__
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] i0s 3'b010");
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`endif
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`endif
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end
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3'b011: Z = C;
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3'b011: Z = C;
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3'b100: Z = P;
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3'b100: begin Z = P;
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`ifdef __ICARUS__
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`ifdef __ICARUS__
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
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if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
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if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
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if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
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`endif
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`endif
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end
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3'b101: Z = $signed(PCIN[47:17]);
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3'b101: Z = $signed(PCIN[47:17]);
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3'b110: Z = $signed(P[47:17]);
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3'b110: Z = $signed(P[47:17]);
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default: Z = 48'bx;
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default: Z = 48'bx;
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endcase
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endcase
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end
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end
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// Carry in
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wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17];
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reg CARRYINr, A24_xnor_B17;
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generate
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if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end
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else always @* CARRYINr = CARRYIN;
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if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CECARRYIN) A24_xnor_B17 <= A24_xnor_B17d; end
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else always @* A24_xnor_B17 = A24_xnor_B17d;
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endgenerate
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reg cin_muxed;
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always @(*) begin
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case (CARRYINSELr)
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3'b000: cin_muxed = CARRYINr;
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3'b001: cin_muxed = ~PCIN[47];
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3'b010: cin_muxed = CARRYCASCIN;
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3'b011: cin_muxed = PCIN[47];
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3'b100: cin_muxed = CARRYCASCOUT;
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3'b101: cin_muxed = ~P[47];
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3'b110: cin_muxed = A24_xnor_B17;
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3'b111: cin_muxed = P[47];
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default: cin_muxed = 1'bx;
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endcase
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end
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wire alu_cin = (ALUMODEr[3] || ALUMODEr[2]) ? 1'b0 : cin_muxed;
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// ALU core
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// ALU core
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wire alu_cin = 1'b0; // FIXME*
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wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z;
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wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z;
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wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv;
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wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv;
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wire [47:0] maj_xyz = (X & Y) | (X & Z) | (X & Y);
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wire [47:0] maj_xyz = (X & Y) | (X & Z) | (X & Y);
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@ -730,16 +744,11 @@ module DSP48E1 (
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endgenerate
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endgenerate
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wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum;
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wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum;
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initial P = 48'b0;
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wire [3:0] CARRYOUTd = (ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out;
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wire [3:0] CARRYOUTd = (ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out;
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wire CARRYCASCOUTd = ext_carry_out[3];
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wire CARRYCASCOUTd = ext_carry_out[3];
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wire MULTSIGNOUTd = Mr[42];
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wire MULTSIGNOUTd = Mr[42];
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always @* begin
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`ifdef __ICARUS__
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if (CARRYINSEL != 3'b000) $fatal(1, "Unsupported CARRYINSEL value");
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`endif
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end
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generate
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generate
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if (PREG == 1) begin
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if (PREG == 1) begin
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always @(posedge CLK)
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always @(posedge CLK)
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@ -4,3 +4,4 @@ bram1_[0-9]*/
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bram2.log
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bram2.log
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bram2_syn.v
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bram2_syn.v
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bram2_tb
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bram2_tb
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dsp_work*/
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@ -0,0 +1,310 @@
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`timescale 1ns / 1ps
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module testbench;
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parameter integer ACASCREG = 1;
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parameter integer ADREG = 1;
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parameter integer ALUMODEREG = 1;
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parameter integer AREG = 1;
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parameter AUTORESET_PATDET = "NO_RESET";
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parameter A_INPUT = "DIRECT";
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parameter integer BCASCREG = 1;
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parameter integer BREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter integer CARRYINREG = 1;
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parameter integer CARRYINSELREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer INMODEREG = 1;
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parameter integer MREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer PREG = 1;
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parameter SEL_MASK = "MASK";
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parameter SEL_PATTERN = "PATTERN";
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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parameter USE_PATTERN_DETECT = "NO_PATDET";
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parameter USE_SIMD = "ONE48";
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parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
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parameter [47:0] PATTERN = 48'h000000000000;
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parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
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parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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parameter [4:0] IS_INMODE_INVERTED = 5'b0;
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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reg CLK;
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reg CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL;
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reg CED, CEINMODE, CEM, CEP;
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reg RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP;
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reg [29:0] A, ACIN;
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reg [17:0] B, BCIN;
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reg [47:0] C;
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reg [24:0] D;
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reg [47:0] PCIN;
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reg [3:0] ALUMODE;
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reg [2:0] CARRYINSEL;
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reg [4:0] INMODE;
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reg [6:0] OPMODE;
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reg CARRYCASCIN, CARRYIN, MULTSIGNIN;
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output [29:0] ACOUT, REF_ACOUT;
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output [17:0] BCOUT, REF_BCOUT;
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output CARRYCASCOUT, REF_CARRYCASCOUT;
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output [3:0] CARRYOUT, REF_CARRYOUT;
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output MULTSIGNOUT, REF_MULTSIGNOUT;
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output OVERFLOW, REF_OVERFLOW;
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output [47:0] P, REF_P;
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output PATTERNBDETECT, REF_PATTERNBDETECT;
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output PATTERNDETECT, REF_PATTERNDETECT;
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output [47:0] PCOUT, REF_PCOUT;
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output UNDERFLOW, REF_UNDERFLOW;
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integer errcount = 0;
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task clkcycle;
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begin
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#5;
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CLK = ~CLK;
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#10;
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CLK = ~CLK;
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#2;
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if (REF_P !== P) begin
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$display("ERROR at %1t: REF_P=%b UUT_P=%b DIFF=%b", $time, REF_P, P, REF_P ^ P);
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errcount = errcount + 1;
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end
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if (REF_CARRYOUT !== CARRYOUT) begin
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$display("ERROR at %1t: REF_CARRYOUT=%b UUT_CARRYOUT=%b", $time, REF_CARRYOUT, CARRYOUT);
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errcount = errcount + 1;
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end
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#3;
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end
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endtask
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reg config_valid = 0;
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task drc;
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config_valid = 1;
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if (AREG != 2 && INMODE[0]) config_valid = 0;
|
||||||
|
if (BREG != 2 && INMODE[4]) config_valid = 0;
|
||||||
|
if ((OPMODE[3:2] == 2'b01) ^ (OPMODE[1:0] == 2'b01) == 1'b1) config_valid = 0;
|
||||||
|
if ((OPMODE[6:4] == 3'b010) && PREG != 1) config_valid = 0;
|
||||||
|
if ((OPMODE[6:4] == 3'b010) && (PREG != 1 || OPMODE[3:0] != 4'b1000)) config_valid = 0;
|
||||||
|
endtask
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
$dumpfile("test_dsp_model.vcd");
|
||||||
|
$dumpvars(0, testbench);
|
||||||
|
|
||||||
|
#2;
|
||||||
|
CLK = 1'b0;
|
||||||
|
{CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL} = 9'b111111111;
|
||||||
|
{CED, CEINMODE, CEM, CEP} = 4'b1111;
|
||||||
|
|
||||||
|
{A, B, C, D} = 0;
|
||||||
|
{ACIN, BCIN, PCIN} = 0;
|
||||||
|
{ALUMODE, CARRYINSEL, INMODE} = 0;
|
||||||
|
{OPMODE, CARRYCASCIN, CARRYIN, MULTSIGNIN} = 0;
|
||||||
|
|
||||||
|
{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = ~0;
|
||||||
|
#5;
|
||||||
|
CLK = 1'b1;
|
||||||
|
#10;
|
||||||
|
CLK = 1'b0
|
||||||
|
#5;
|
||||||
|
CLK = 1'b1;
|
||||||
|
#10;
|
||||||
|
CLK = 1'b0;
|
||||||
|
{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = 0;
|
||||||
|
|
||||||
|
repeat (300) begin
|
||||||
|
clkcycle;
|
||||||
|
do begin
|
||||||
|
A = $urandom;
|
||||||
|
ACIN = $urandom;
|
||||||
|
B = $urandom;
|
||||||
|
BCIN = $urandom;
|
||||||
|
C = {$urandom, $urandom};
|
||||||
|
D = $urandom;
|
||||||
|
PCIN = {$urandom, $urandom};
|
||||||
|
|
||||||
|
{RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom;
|
||||||
|
{ALUMODE, CARRYINSEL, INMODE} = $urandom & $urandom & $urandom;
|
||||||
|
OPMODE = $urandom;
|
||||||
|
{CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom;
|
||||||
|
drc;
|
||||||
|
end while (!config_valid);
|
||||||
|
end
|
||||||
|
|
||||||
|
if (errcount == 0) begin
|
||||||
|
$display("All tests passed.");
|
||||||
|
$finish;
|
||||||
|
end else begin
|
||||||
|
$display("Caught %1d errors.", errcount);
|
||||||
|
$stop;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
DSP48E1 #(
|
||||||
|
.ACASCREG (ACASCREG),
|
||||||
|
.ADREG (ADREG),
|
||||||
|
.ALUMODEREG (ALUMODEREG),
|
||||||
|
.AREG (AREG),
|
||||||
|
.AUTORESET_PATDET (AUTORESET_PATDET),
|
||||||
|
.A_INPUT (A_INPUT),
|
||||||
|
.BCASCREG (BCASCREG),
|
||||||
|
.BREG (BREG),
|
||||||
|
.B_INPUT (B_INPUT),
|
||||||
|
.CARRYINREG (CARRYINREG),
|
||||||
|
.CARRYINSELREG (CARRYINSELREG),
|
||||||
|
.CREG (CREG),
|
||||||
|
.DREG (DREG),
|
||||||
|
.INMODEREG (INMODEREG),
|
||||||
|
.MREG (MREG),
|
||||||
|
.OPMODEREG (OPMODEREG),
|
||||||
|
.PREG (PREG),
|
||||||
|
.SEL_MASK (SEL_MASK),
|
||||||
|
.SEL_PATTERN (SEL_PATTERN),
|
||||||
|
.USE_DPORT (USE_DPORT),
|
||||||
|
.USE_MULT (USE_MULT),
|
||||||
|
.USE_PATTERN_DETECT (USE_PATTERN_DETECT),
|
||||||
|
.USE_SIMD (USE_SIMD),
|
||||||
|
.MASK (MASK),
|
||||||
|
.PATTERN (PATTERN),
|
||||||
|
.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
|
||||||
|
.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
|
||||||
|
.IS_CLK_INVERTED (IS_CLK_INVERTED),
|
||||||
|
.IS_INMODE_INVERTED (IS_INMODE_INVERTED),
|
||||||
|
.IS_OPMODE_INVERTED (IS_OPMODE_INVERTED)
|
||||||
|
) ref (
|
||||||
|
.ACOUT (REF_ACOUT),
|
||||||
|
.BCOUT (REF_BCOUT),
|
||||||
|
.CARRYCASCOUT (REF_CARRYCASCOUT),
|
||||||
|
.CARRYOUT (REF_CARRYOUT),
|
||||||
|
.MULTSIGNOUT (REF_MULTSIGNOUT),
|
||||||
|
.OVERFLOW (REF_OVERFLOW),
|
||||||
|
.P (REF_P),
|
||||||
|
.PATTERNBDETECT(REF_PATTERNBDETECT),
|
||||||
|
.PATTERNDETECT (REF_PATTERNDETECT),
|
||||||
|
.PCOUT (REF_PCOUT),
|
||||||
|
.UNDERFLOW (REF_UNDERFLOW),
|
||||||
|
.A (A),
|
||||||
|
.ACIN (ACIN),
|
||||||
|
.ALUMODE (ALUMODE),
|
||||||
|
.B (B),
|
||||||
|
.BCIN (BCIN),
|
||||||
|
.C (C),
|
||||||
|
.CARRYCASCIN (CARRYCASCIN),
|
||||||
|
.CEA1 (CEA1),
|
||||||
|
.CEA2 (CEA2),
|
||||||
|
.CEAD (CEAD),
|
||||||
|
.CEALUMODE (CEALUMODE),
|
||||||
|
.CEB1 (CEB1),
|
||||||
|
.CEB2 (CEB2),
|
||||||
|
.CEC (CEC),
|
||||||
|
.CECARRYIN (CECARRYIN),
|
||||||
|
.CECTRL (CECTRL),
|
||||||
|
.CED (CED),
|
||||||
|
.CEINMODE (CEINMODE),
|
||||||
|
.CEM (CEM),
|
||||||
|
.CEP (CEP),
|
||||||
|
.CLK (CLK),
|
||||||
|
.D (D),
|
||||||
|
.INMODE (INMODE),
|
||||||
|
.MULTSIGNIN (MULTSIGNIN),
|
||||||
|
.OPMODE (OPMODE),
|
||||||
|
.PCIN (PCIN),
|
||||||
|
.RSTA (RSTA),
|
||||||
|
.RSTALLCARRYIN (RSTALLCARRYIN),
|
||||||
|
.RSTALUMODE (RSTALUMODE),
|
||||||
|
.RSTB (RSTB),
|
||||||
|
.RSTC (RSTC),
|
||||||
|
.RSTCTRL (RSTCTRL),
|
||||||
|
.RSTD (RSTD),
|
||||||
|
.RSTINMODE (RSTINMODE),
|
||||||
|
.RSTM (RSTM),
|
||||||
|
.RSTP (RSTP)
|
||||||
|
);
|
||||||
|
|
||||||
|
DSP48E1_UUT #(
|
||||||
|
.ACASCREG (ACASCREG),
|
||||||
|
.ADREG (ADREG),
|
||||||
|
.ALUMODEREG (ALUMODEREG),
|
||||||
|
.AREG (AREG),
|
||||||
|
.AUTORESET_PATDET (AUTORESET_PATDET),
|
||||||
|
.A_INPUT (A_INPUT),
|
||||||
|
.BCASCREG (BCASCREG),
|
||||||
|
.BREG (BREG),
|
||||||
|
.B_INPUT (B_INPUT),
|
||||||
|
.CARRYINREG (CARRYINREG),
|
||||||
|
.CARRYINSELREG (CARRYINSELREG),
|
||||||
|
.CREG (CREG),
|
||||||
|
.DREG (DREG),
|
||||||
|
.INMODEREG (INMODEREG),
|
||||||
|
.MREG (MREG),
|
||||||
|
.OPMODEREG (OPMODEREG),
|
||||||
|
.PREG (PREG),
|
||||||
|
.SEL_MASK (SEL_MASK),
|
||||||
|
.SEL_PATTERN (SEL_PATTERN),
|
||||||
|
.USE_DPORT (USE_DPORT),
|
||||||
|
.USE_MULT (USE_MULT),
|
||||||
|
.USE_PATTERN_DETECT (USE_PATTERN_DETECT),
|
||||||
|
.USE_SIMD (USE_SIMD),
|
||||||
|
.MASK (MASK),
|
||||||
|
.PATTERN (PATTERN),
|
||||||
|
.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
|
||||||
|
.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
|
||||||
|
.IS_CLK_INVERTED (IS_CLK_INVERTED),
|
||||||
|
.IS_INMODE_INVERTED (IS_INMODE_INVERTED),
|
||||||
|
.IS_OPMODE_INVERTED (IS_OPMODE_INVERTED)
|
||||||
|
) uut (
|
||||||
|
.ACOUT (ACOUT),
|
||||||
|
.BCOUT (BCOUT),
|
||||||
|
.CARRYCASCOUT (CARRYCASCOUT),
|
||||||
|
.CARRYOUT (CARRYOUT),
|
||||||
|
.MULTSIGNOUT (MULTSIGNOUT),
|
||||||
|
.OVERFLOW (OVERFLOW),
|
||||||
|
.P (P),
|
||||||
|
.PATTERNBDETECT(PATTERNBDETECT),
|
||||||
|
.PATTERNDETECT (PATTERNDETECT),
|
||||||
|
.PCOUT (PCOUT),
|
||||||
|
.UNDERFLOW (UNDERFLOW),
|
||||||
|
.A (A),
|
||||||
|
.ACIN (ACIN),
|
||||||
|
.ALUMODE (ALUMODE),
|
||||||
|
.B (B),
|
||||||
|
.BCIN (BCIN),
|
||||||
|
.C (C),
|
||||||
|
.CARRYCASCIN (CARRYCASCIN),
|
||||||
|
.CEA1 (CEA1),
|
||||||
|
.CEA2 (CEA2),
|
||||||
|
.CEAD (CEAD),
|
||||||
|
.CEALUMODE (CEALUMODE),
|
||||||
|
.CEB1 (CEB1),
|
||||||
|
.CEB2 (CEB2),
|
||||||
|
.CEC (CEC),
|
||||||
|
.CECARRYIN (CECARRYIN),
|
||||||
|
.CECTRL (CECTRL),
|
||||||
|
.CED (CED),
|
||||||
|
.CEINMODE (CEINMODE),
|
||||||
|
.CEM (CEM),
|
||||||
|
.CEP (CEP),
|
||||||
|
.CLK (CLK),
|
||||||
|
.D (D),
|
||||||
|
.INMODE (INMODE),
|
||||||
|
.MULTSIGNIN (MULTSIGNIN),
|
||||||
|
.OPMODE (OPMODE),
|
||||||
|
.PCIN (PCIN),
|
||||||
|
.RSTA (RSTA),
|
||||||
|
.RSTALLCARRYIN (RSTALLCARRYIN),
|
||||||
|
.RSTALUMODE (RSTALUMODE),
|
||||||
|
.RSTB (RSTB),
|
||||||
|
.RSTC (RSTC),
|
||||||
|
.RSTCTRL (RSTCTRL),
|
||||||
|
.RSTD (RSTD),
|
||||||
|
.RSTINMODE (RSTINMODE),
|
||||||
|
.RSTM (RSTM),
|
||||||
|
.RSTP (RSTP)
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
Loading…
Reference in New Issue