mirror of https://github.com/YosysHQ/yosys.git
Add split_shiftx command
This commit is contained in:
Eddie Hung
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8d00b9ef7e
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ccd0729456
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "passes/pmgen/split_shiftx_pm.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void create_split_shiftx(split_shiftx_pm &pm)
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{
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if (pm.st.shiftxB.empty())
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return;
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log_assert(pm.st.shiftx);
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SigSpec A = pm.st.shiftx->getPort("\\A");
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SigSpec Y = pm.st.shiftx->getPort("\\Y");
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const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int();
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const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int();
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log_assert(Y_WIDTH > 1);
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std::vector<SigBit> bits;
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bits.resize(A_WIDTH / Y_WIDTH);
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for (int i = 0; i < Y_WIDTH; ++i) {
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for (int j = 0; j < A_WIDTH/Y_WIDTH; ++j)
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bits[j] = A[j*Y_WIDTH + i];
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pm.module->addShiftx(NEW_ID, bits, pm.st.shiftxB, Y[i]);
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}
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pm.st.shiftx->unsetPort("\\Y");
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pm.autoremove(pm.st.shiftx);
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pm.autoremove(pm.st.macc);
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}
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struct BitblastShiftxPass : public Pass {
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BitblastShiftxPass() : Pass("split_shiftx", "Split up multi-bit $shiftx cells") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" split_shiftx [selection]\n");
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log("\n");
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log("Split up $shiftx cells where Y_WIDTH > 1, with consideration for any $macc\n");
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log("cells that may be driving their B inputs.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing SPLIT_SHIFTX pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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split_shiftx_pm(module, module->selected_cells()).run(create_split_shiftx);
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}
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} BitblastShiftxPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,56 @@
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state <SigSpec> shiftxB
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match shiftx
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select shiftx->type == $shiftx
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select param(shiftx, \Y_WIDTH).as_int() > 1
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endmatch
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code shiftxB
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shiftxB = port(shiftx, \B);
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const int b_width = param(shiftx, \B_WIDTH).as_int();
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if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
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shiftxB = shiftxB.extract(0, b_width-1);
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endcode
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match macc
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select macc->type == $macc
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select param(macc, \B_WIDTH).as_int() == 0
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index <SigSpec> port(macc, \Y) === shiftxB
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optional
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endmatch
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code shiftxB
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if (macc) {
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Const config = param(macc, \CONFIG);
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const int config_width = param(macc, \CONFIG_WIDTH).as_int();
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const int num_bits = config.extract(0, 4).as_int();
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const int num_ports = (config_width - 4) / (2 + 2*num_bits);
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if (num_ports != 1) {
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shiftxB = nullptr;
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reject;
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}
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// IS_SIGNED?
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if (config[4] == 1) {
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shiftxB = nullptr;
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reject;
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}
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// DO_SUBTRACT?
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if (config[5] == 1) {
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shiftxB = nullptr;
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reject;
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}
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const int port_size_A = config.extract(6, num_bits).as_int();
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const int port_size_B = config.extract(6 + num_bits, num_bits).as_int();
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const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B);
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if (!port_B.is_fully_const()) {
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shiftxB = nullptr;
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reject;
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}
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const int multiply_factor = port_B.as_int();
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if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) {
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shiftxB = nullptr;
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reject;
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}
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shiftxB = port(macc, \A).extract(0, port_size_A);
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}
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endcode
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