riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

verific: unflatten struct ports

This commit is contained in:
Eddie Hung 2020-01-24 10:12:52 -08:00
parent da6abc0149
commit cccc0ae112
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
frontends/verific/verific.cc
View File

@ -2470,6 +2470,9 @@ struct VerificPass : public Pass {
worker.run(nl); worker.run(nl);
} }
for (auto nl : nl_todo)
nl->ChangePortBusStructures(1 /* hierarchical */);
if (!dumpfile.empty()) { if (!dumpfile.empty()) {
VeriWrite veri_writer; VeriWrite veri_writer;
veri_writer.WriteFile(dumpfile.c_str(), Netlist::PresentDesign()); veri_writer.WriteFile(dumpfile.c_str(), Netlist::PresentDesign());