riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added RTLIL NEW_WIRE macro

This commit is contained in:
Clifford Wolf 2013-10-18 13:25:24 +02:00
parent 0836a1f2ba
commit cc5e379eca
2 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
kernel/rtlil.cc
View File

@ -382,6 +382,15 @@ RTLIL::Module *RTLIL::Module::clone() const
return new_mod; return new_mod;
} }
RTLIL::SigSpec RTLIL::Module::new_wire(int width, RTLIL::IdString name)
{
RTLIL::Wire *wire = new RTLIL::Wire;
wire->width = width;
wire->name = name;
add(wire);
return wire;
}
void RTLIL::Module::add(RTLIL::Wire *wire) void RTLIL::Module::add(RTLIL::Wire *wire)
{ {
assert(!wire->name.empty()); assert(!wire->name.empty());

4
kernel/rtlil.h
View File

@ -129,6 +129,9 @@ namespace RTLIL
#define NEW_ID \ #define NEW_ID \
RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__) RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__)
#define NEW_WIRE(_mod, _width) \
(_mod)->new_wire(_width, NEW_ID)
template <typename T> struct sort_by_name { template <typename T> struct sort_by_name {
bool operator()(T *a, T *b) const { bool operator()(T *a, T *b) const {
return a->name < b->name; return a->name < b->name;
@ -244,6 +247,7 @@ struct RTLIL::Module {
virtual size_t count_id(RTLIL::IdString id); virtual size_t count_id(RTLIL::IdString id);
virtual void check(); virtual void check();
virtual void optimize(); virtual void optimize();
RTLIL::SigSpec new_wire(int width, RTLIL::IdString name);
void add(RTLIL::Wire *wire); void add(RTLIL::Wire *wire);
void add(RTLIL::Cell *cell); void add(RTLIL::Cell *cell);
void fixup_ports(); void fixup_ports();