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Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width 

opt_demorgan: skip zero width cells
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Emil J 2024-11-20 13:33:16 +01:00 committed by GitHub
parent 18459b4b09 e105cae4a9
commit cc17d5bb70
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2 changed files with 19 additions and 0 deletions
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4
passes/opt/opt_demorgan.cc
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@ -39,6 +39,10 @@ void demorgan_worker(
return; return;
auto insig = sigmap(cell->getPort(ID::A)); auto insig = sigmap(cell->getPort(ID::A));
if (GetSize(insig) < 1)
return;
log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig)); log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
int num_inverted = 0; int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++) for(int i=0; i<GetSize(insig); i++)

15
tests/opt/bug4610.ys Normal file
View File

@ -0,0 +1,15 @@
read_ilang <<EOT
autoidx 1
module \top
wire output 1 \Y
cell $reduce_or $reduce_or$rtl.v:29$20
parameter \A_SIGNED 0
parameter \A_WIDTH 0
parameter \Y_WIDTH 1
connect \A { }
connect \Y \Y
end
end
EOT
equiv_opt -assert opt_demorgan