mirror of https://github.com/YosysHQ/yosys.git
cellmatch: Visit whiteboxes for `-derive_luts`
This commit is contained in:
parent
c9ed6d8dcf
commit
cbe73c9047
|
@ -214,7 +214,7 @@ struct CellmatchPass : Pass {
|
|||
r.first->second = new Design;
|
||||
Design *map_design = r.first->second;
|
||||
|
||||
for (auto m : d->selected_whole_modules_warn()) {
|
||||
for (auto m : d->selected_whole_modules_warn(/* visit whiteboxes */derive_luts)) {
|
||||
std::vector<uint64_t> luts;
|
||||
if (!derive_module_luts(m, luts))
|
||||
continue;
|
||||
|
|
Loading…
Reference in New Issue