mirror of https://github.com/YosysHQ/yosys.git
rtlil: Fix macc_v2 cell check
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1e8aa56f7f
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cb8f855f34
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@ -1472,16 +1472,16 @@ namespace {
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error(__LINE__);
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error(__LINE__);
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if (param(ID::NADDENDS) <= 0)
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if (param(ID::NADDENDS) <= 0)
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error(__LINE__);
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error(__LINE__);
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param_bits(ID::PRODUCT_NEGATED, min(param(ID::NPRODUCTS), 1));
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param_bits(ID::PRODUCT_NEGATED, max(param(ID::NPRODUCTS), 1));
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param_bits(ID::ADDEND_NEGATED, min(param(ID::NADDENDS), 1));
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param_bits(ID::ADDEND_NEGATED, max(param(ID::NADDENDS), 1));
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param_bits(ID::A_SIGNED, min(param(ID::NPRODUCTS), 1));
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param_bits(ID::A_SIGNED, max(param(ID::NPRODUCTS), 1));
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param_bits(ID::B_SIGNED, min(param(ID::NPRODUCTS), 1));
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param_bits(ID::B_SIGNED, max(param(ID::NPRODUCTS), 1));
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param_bits(ID::C_SIGNED, min(param(ID::NADDENDS), 1));
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param_bits(ID::C_SIGNED, max(param(ID::NADDENDS), 1));
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if (cell->getParam(ID::A_SIGNED) != cell->getParam(ID::B_SIGNED))
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if (cell->getParam(ID::A_SIGNED) != cell->getParam(ID::B_SIGNED))
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error(__LINE__);
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error(__LINE__);
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param_bits(ID::A_WIDTHS, min(param(ID::NPRODUCTS) * 16, 1));
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param_bits(ID::A_WIDTHS, max(param(ID::NPRODUCTS) * 16, 1));
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param_bits(ID::B_WIDTHS, min(param(ID::NPRODUCTS) * 16, 1));
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param_bits(ID::B_WIDTHS, max(param(ID::NPRODUCTS) * 16, 1));
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param_bits(ID::C_WIDTHS, min(param(ID::NADDENDS) * 16, 1));
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param_bits(ID::C_WIDTHS, max(param(ID::NADDENDS) * 16, 1));
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const Const &a_width = cell->getParam(ID::A_WIDTHS);
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const Const &a_width = cell->getParam(ID::A_WIDTHS);
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const Const &b_width = cell->getParam(ID::B_WIDTHS);
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const Const &b_width = cell->getParam(ID::B_WIDTHS);
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const Const &c_width = cell->getParam(ID::C_WIDTHS);
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const Const &c_width = cell->getParam(ID::C_WIDTHS);
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