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Merge pull request #2269 from YosysHQ/claire/bisonwall 

Use "bison -Wall -Werror" for verilog front-end
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whitequark 2020-07-15 19:20:33 +00:00 committed by GitHub
parent 021ce8e596 51ee0b683f
commit cb757b28b4
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 57 additions and 64 deletions
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2
frontends/verilog/Makefile.inc
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@ -6,7 +6,7 @@ GENFILES += frontends/verilog/verilog_lexer.cc
frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
$(Q) mkdir -p $(dir $@) $(Q) mkdir -p $(dir $@)
$(P) $(BISON) -Werror=conflicts-sr,error=conflicts-rr -o $@ -d -r all -b frontends/verilog/verilog_parser $< $(P) $(BISON) -Wall -Werror -o $@ -d -r all -b frontends/verilog/verilog_parser $<
frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc

119
frontends/verilog/verilog_parser.y
View File

@ -299,14 +299,14 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%left '+' '-' %left '+' '-'
%left '*' '/' '%' %left '*' '/' '%'
%left OP_POW %left OP_POW
%left OP_CAST %precedence OP_CAST
%right UNARY_OPS %precedence UNARY_OPS
%define parse.error verbose %define parse.error verbose
%define parse.lac full %define parse.lac full
%nonassoc FAKE_THEN %precedence FAKE_THEN
%nonassoc TOK_ELSE %precedence TOK_ELSE
%debug %debug
%locations %locations
@ -333,7 +333,7 @@ design:
typedef_decl design | typedef_decl design |
package design | package design |
interface design | interface design |
/* empty */; %empty;
attr: attr:
{ {
@ -355,7 +355,7 @@ attr_opt:
attr_opt ATTR_BEGIN opt_attr_list ATTR_END { attr_opt ATTR_BEGIN opt_attr_list ATTR_END {
SET_RULE_LOC(@$, @2, @$); SET_RULE_LOC(@$, @2, @$);
}| }|
/* empty */; %empty;
defattr: defattr:
DEFATTR_BEGIN { DEFATTR_BEGIN {
@ -376,7 +376,7 @@ defattr:
} DEFATTR_END; } DEFATTR_END;
opt_attr_list: opt_attr_list:
attr_list | /* empty */; attr_list | %empty;
attr_list: attr_list:
attr_assign | attr_assign |
@ -449,13 +449,13 @@ module:
}; };
module_para_opt: module_para_opt:
'#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | /* empty */; '#' '(' { astbuf1 = nullptr; } module_para_list { if (astbuf1) delete astbuf1; } ')' | %empty;
module_para_list: module_para_list:
single_module_para | module_para_list ',' single_module_para; single_module_para | module_para_list ',' single_module_para;
single_module_para: single_module_para:
/* empty */ | %empty |
attr TOK_PARAMETER { attr TOK_PARAMETER {
if (astbuf1) delete astbuf1; if (astbuf1) delete astbuf1;
astbuf1 = new AstNode(AST_PARAMETER); astbuf1 = new AstNode(AST_PARAMETER);
@ -471,13 +471,13 @@ single_module_para:
single_param_decl; single_param_decl;
module_args_opt: module_args_opt:
'(' ')' | /* empty */ | '(' module_args optional_comma ')'; '(' ')' | %empty | '(' module_args optional_comma ')';
module_args: module_args:
module_arg | module_args ',' module_arg; module_arg | module_args ',' module_arg;
optional_comma: optional_comma:
',' | /* empty */; ',' | %empty;
module_arg_opt_assignment: module_arg_opt_assignment:
'=' expr { '=' expr {
@ -497,7 +497,7 @@ module_arg_opt_assignment:
} else } else
frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value."); frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
} | } |
/* empty */; %empty;
module_arg: module_arg:
TOK_ID { TOK_ID {
@ -565,15 +565,10 @@ package:
}; };
package_body: package_body:
package_body package_body_stmt package_body package_body_stmt | %empty;
| // optional
;
package_body_stmt: package_body_stmt:
typedef_decl typedef_decl | localparam_decl | param_decl;
| localparam_decl
| param_decl
;
interface: interface:
TOK_INTERFACE { TOK_INTERFACE {
@ -599,7 +594,7 @@ interface:
}; };
interface_body: interface_body:
interface_body interface_body_stmt |; interface_body interface_body_stmt | %empty;
interface_body_stmt: interface_body_stmt:
param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt | param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
@ -613,7 +608,7 @@ non_opt_delay:
'#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; }; '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };
delay: delay:
non_opt_delay | /* empty */; non_opt_delay | %empty;
wire_type: wire_type:
{ {
@ -725,7 +720,7 @@ range:
non_opt_range { non_opt_range {
$$ = $1; $$ = $1;
} | } |
/* empty */ { %empty {
$$ = NULL; $$ = NULL;
}; };
@ -743,7 +738,7 @@ module_body:
/* the following line makes the generate..endgenrate keywords optional */ /* the following line makes the generate..endgenrate keywords optional */
module_body gen_stmt | module_body gen_stmt |
module_body ';' | module_body ';' |
/* empty */; %empty;
module_body_stmt: module_body_stmt:
task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
@ -843,28 +838,28 @@ dpi_function_arg:
opt_dpi_function_args: opt_dpi_function_args:
'(' dpi_function_args ')' | '(' dpi_function_args ')' |
/* empty */; %empty;
dpi_function_args: dpi_function_args:
dpi_function_args ',' dpi_function_arg | dpi_function_args ',' dpi_function_arg |
dpi_function_args ',' | dpi_function_args ',' |
dpi_function_arg | dpi_function_arg |
/* empty */; %empty;
opt_automatic: opt_automatic:
TOK_AUTOMATIC | TOK_AUTOMATIC |
/* empty */; %empty;
opt_signed: opt_signed:
TOK_SIGNED { TOK_SIGNED {
$$ = true; $$ = true;
} | } |
/* empty */ { %empty {
$$ = false; $$ = false;
}; };
task_func_args_opt: task_func_args_opt:
'(' ')' | /* empty */ | '(' { '(' ')' | %empty | '(' {
albuf = nullptr; albuf = nullptr;
astbuf1 = nullptr; astbuf1 = nullptr;
astbuf2 = nullptr; astbuf2 = nullptr;
@ -905,7 +900,7 @@ task_func_port:
task_func_body: task_func_body:
task_func_body behavioral_stmt | task_func_body behavioral_stmt |
/* empty */; %empty;
/*************************** specify parser ***************************/ /*************************** specify parser ***************************/
@ -914,7 +909,7 @@ specify_block:
specify_item_list: specify_item_list:
specify_item specify_item_list | specify_item specify_item_list |
/* empty */; %empty;
specify_item: specify_item:
specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' { specify_if '(' specify_edge expr TOK_SPECIFY_OPER specify_target ')' '=' specify_rise_fall ';' {
@ -1076,7 +1071,7 @@ specify_opt_triple:
',' specify_triple { ',' specify_triple {
$$ = $2; $$ = $2;
} | } |
/* empty */ { %empty {
$$ = nullptr; $$ = nullptr;
}; };
@ -1084,7 +1079,7 @@ specify_if:
TOK_IF '(' expr ')' { TOK_IF '(' expr ')' {
$$ = $3; $$ = $3;
} | } |
/* empty */ { %empty {
$$ = nullptr; $$ = nullptr;
}; };
@ -1092,7 +1087,7 @@ specify_condition:
TOK_SPECIFY_AND expr { TOK_SPECIFY_AND expr {
$$ = $2; $$ = $2;
} | } |
/* empty */ { %empty {
$$ = nullptr; $$ = nullptr;
}; };
@ -1125,7 +1120,7 @@ specify_target:
specify_edge: specify_edge:
TOK_POSEDGE { $$ = 'p'; } | TOK_POSEDGE { $$ = 'p'; } |
TOK_NEGEDGE { $$ = 'n'; } | TOK_NEGEDGE { $$ = 'n'; } |
{ $$ = 0; }; %empty { $$ = 0; };
specify_rise_fall: specify_rise_fall:
specify_triple { specify_triple {
@ -1232,7 +1227,7 @@ specparam_assignment:
ignspec_id '=' ignspec_expr ; ignspec_id '=' ignspec_expr ;
ignspec_opt_cond: ignspec_opt_cond:
TOK_IF '(' ignspec_expr ')' | /* empty */; TOK_IF '(' ignspec_expr ')' | %empty;
path_declaration : path_declaration :
simple_path_declaration ';' simple_path_declaration ';'
@ -1283,9 +1278,7 @@ list_of_path_outputs :
list_of_path_outputs ',' specify_output_terminal_descriptor ; list_of_path_outputs ',' specify_output_terminal_descriptor ;
opt_polarity_operator : opt_polarity_operator :
'+' '+' | '-' | %empty;
| '-'
| ;
// Good enough for the time being // Good enough for the time being
specify_input_terminal_descriptor : specify_input_terminal_descriptor :
@ -1334,7 +1327,7 @@ param_signed:
astbuf1->is_signed = true; astbuf1->is_signed = true;
} | TOK_UNSIGNED { } | TOK_UNSIGNED {
astbuf1->is_signed = false; astbuf1->is_signed = false;
} | /* empty */; } | %empty;
param_integer: param_integer:
TOK_INTEGER { TOK_INTEGER {
@ -1451,7 +1444,7 @@ enum_type: TOK_ENUM {
enum_base_type: type_atom type_signing enum_base_type: type_atom type_signing
| type_vec type_signing range { if ($3) astbuf1->children.push_back($3); } | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
| /* nothing */ { astbuf1->is_reg = true; addRange(astbuf1); } | %empty { astbuf1->is_reg = true; addRange(astbuf1); }
; ;
type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
@ -1467,7 +1460,7 @@ type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
type_signing: type_signing:
TOK_SIGNED { astbuf1->is_signed = true; } TOK_SIGNED { astbuf1->is_signed = true; }
| TOK_UNSIGNED { astbuf1->is_signed = false; } | TOK_UNSIGNED { astbuf1->is_signed = false; }
| // optional | %empty
; ;
enum_name_list: enum_name_decl enum_name_list: enum_name_decl
@ -1491,7 +1484,7 @@ enum_name_decl:
opt_enum_init: opt_enum_init:
'=' basic_expr { $$ = $2; } // TODO: restrict this '=' basic_expr { $$ = $2; } // TODO: restrict this
| /* optional */ { $$ = NULL; } | %empty { $$ = NULL; }
; ;
enum_var_list: enum_var_list:
@ -1532,14 +1525,14 @@ struct_union:
struct_body: opt_packed '{' struct_member_list '}' struct_body: opt_packed '{' struct_member_list '}'
; ;
opt_packed: TOK_PACKED opt_signed_struct opt_packed:
| { frontend_verilog_yyerror("Only PACKED supported at this time"); } TOK_PACKED opt_signed_struct |
; %empty { frontend_verilog_yyerror("Only PACKED supported at this time"); };
opt_signed_struct: opt_signed_struct:
TOK_SIGNED { astbuf2->is_signed = true; } TOK_SIGNED { astbuf2->is_signed = true; }
| TOK_UNSIGNED { astbuf2->is_signed = false; } | TOK_UNSIGNED { astbuf2->is_signed = false; }
| // default is unsigned | %empty // default is unsigned
; ;
struct_member_list: struct_member struct_member_list: struct_member
@ -1646,7 +1639,7 @@ wire_decl:
} opt_supply_wires ';'; } opt_supply_wires ';';
opt_supply_wires: opt_supply_wires:
/* empty */ | %empty |
opt_supply_wires ',' TOK_ID { opt_supply_wires ',' TOK_ID {
AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone(); AstNode *wire_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-2)->clone();
AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone(); AstNode *assign_node = ast_stack.back()->children.at(GetSize(ast_stack.back()->children)-1)->clone();
@ -1877,13 +1870,13 @@ single_prim:
} }
cell_parameter_list_opt: cell_parameter_list_opt:
'#' '(' cell_parameter_list ')' | /* empty */; '#' '(' cell_parameter_list ')' | %empty;
cell_parameter_list: cell_parameter_list:
cell_parameter | cell_parameter_list ',' cell_parameter; cell_parameter | cell_parameter_list ',' cell_parameter;
cell_parameter: cell_parameter:
/* empty */ | %empty |
expr { expr {
AstNode *node = new AstNode(AST_PARASET); AstNode *node = new AstNode(AST_PARASET);
astbuf1->children.push_back(node); astbuf1->children.push_back(node);
@ -2041,7 +2034,7 @@ always_cond:
'@' ATTR_BEGIN ')' | '@' ATTR_BEGIN ')' |
'@' '(' ATTR_END | '@' '(' ATTR_END |
'@' '*' | '@' '*' |
/* empty */; %empty;
always_events: always_events:
always_event | always_event |
@ -2071,7 +2064,7 @@ opt_label:
':' TOK_ID { ':' TOK_ID {
$$ = $2; $$ = $2;
} | } |
/* empty */ { %empty {
$$ = NULL; $$ = NULL;
}; };
@ -2079,7 +2072,7 @@ opt_sva_label:
TOK_SVA_LABEL ':' { TOK_SVA_LABEL ':' {
$$ = $1; $$ = $1;
} | } |
/* empty */ { %empty {
$$ = NULL; $$ = NULL;
}; };
@ -2090,7 +2083,7 @@ opt_property:
TOK_FINAL { TOK_FINAL {
$$ = false; $$ = false;
} | } |
/* empty */ { %empty {
$$ = false; $$ = false;
}; };
@ -2501,7 +2494,7 @@ behavioral_stmt:
}; };
unique_case_attr: unique_case_attr:
/* empty */ { %empty {
$$ = false; $$ = false;
} | } |
TOK_PRIORITY case_attr { TOK_PRIORITY case_attr {
@ -2537,11 +2530,11 @@ opt_synopsys_attr:
if (ast_stack.back()->attributes.count(ID::parallel_case) == 0) if (ast_stack.back()->attributes.count(ID::parallel_case) == 0)
ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false); ast_stack.back()->attributes[ID::parallel_case] = AstNode::mkconst_int(1, false);
} | } |
/* empty */; %empty;
behavioral_stmt_list: behavioral_stmt_list:
behavioral_stmt_list behavioral_stmt | behavioral_stmt_list behavioral_stmt |
/* empty */; %empty;
optional_else: optional_else:
TOK_ELSE { TOK_ELSE {
@ -2555,11 +2548,11 @@ optional_else:
} behavioral_stmt { } behavioral_stmt {
SET_AST_NODE_LOC(ast_stack.back(), @3, @3); SET_AST_NODE_LOC(ast_stack.back(), @3, @3);
} | } |
/* empty */ %prec FAKE_THEN; %empty %prec FAKE_THEN;
case_body: case_body:
case_body case_item | case_body case_item |
/* empty */; %empty;
case_item: case_item:
{ {
@ -2582,7 +2575,7 @@ case_item:
gen_case_body: gen_case_body:
gen_case_body gen_case_item | gen_case_body gen_case_item |
/* empty */; %empty;
gen_case_item: gen_case_item:
{ {
@ -2666,11 +2659,11 @@ lvalue_concat_list:
opt_arg_list: opt_arg_list:
'(' arg_list optional_comma ')' | '(' arg_list optional_comma ')' |
/* empty */; %empty;
arg_list: arg_list:
arg_list2 | arg_list2 |
/* empty */; %empty;
arg_list2: arg_list2:
single_arg | single_arg |
@ -2683,7 +2676,7 @@ single_arg:
module_gen_body: module_gen_body:
module_gen_body gen_stmt_or_module_body_stmt | module_gen_body gen_stmt_or_module_body_stmt |
/* empty */; %empty;
gen_stmt_or_module_body_stmt: gen_stmt_or_module_body_stmt:
gen_stmt | module_body_stmt | gen_stmt | module_body_stmt |
@ -2762,7 +2755,7 @@ gen_stmt_block:
}; };
opt_gen_else: opt_gen_else:
TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN; TOK_ELSE gen_stmt_block | %empty %prec FAKE_THEN;
expr: expr:
basic_expr { basic_expr {