riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed sharing of reduce operator

This commit is contained in:
Clifford Wolf 2014-08-08 14:24:09 +02:00
parent 7c94024fc3
commit cb6ca08a53
1 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
passes/sat/share.cc
View File

@ -252,6 +252,19 @@ struct ShareWorker
if (config.generic_uni_ops.count(c1->type)) if (config.generic_uni_ops.count(c1->type))
{ {
if (c1->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool") && c1->getParam("\\A_WIDTH").as_int() != c2->getParam("\\A_WIDTH").as_int())
{
RTLIL::SigBit extbit = c1->type == "$reduce_and" ? RTLIL::State::S1 : RTLIL::State::S0;
while (c1->getParam("\\A_WIDTH").as_int() < c2->getParam("\\A_WIDTH").as_int()) {
c1->setParam("\\A_WIDTH", c1->getParam("\\A_WIDTH").as_int() + 1);
c1->setPort("\\A", {extbit, c1->getPort("\\A")});
}
while (c2->getParam("\\A_WIDTH").as_int() < c1->getParam("\\A_WIDTH").as_int()) {
c2->setParam("\\A_WIDTH", c2->getParam("\\A_WIDTH").as_int() + 1);
c2->setPort("\\A", {extbit, c2->getPort("\\A")});
}
}
if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
{ {
RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;