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Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-05-28 15:33:47 +02:00
parent 2a11c48782
commit cb285e4b87
2 changed files with 15 additions and 4 deletions
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15
passes/pmgen/peepopt_shiftmul.pmg
View File

@ -1,4 +1,7 @@
pattern shiftmul pattern shiftmul
//
// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
//
state <SigSpec> shamt state <SigSpec> shamt
@ -49,12 +52,16 @@ code
if (GetSize(port(shift, \Y)) > const_factor) if (GetSize(port(shift, \Y)) > const_factor)
reject; reject;
int factor_bits = ceil_log2(const_factor);
SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
if (GetSize(shamt) < factor_bits+GetSize(mul_din))
reject;
did_something = true; did_something = true;
log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
int new_const_factor_log2 = ceil_log2(const_factor); int new_const_factor = 1 << factor_bits;
int new_const_factor = 1 << new_const_factor_log2;
SigSpec padding(State::Sx, new_const_factor-const_factor); SigSpec padding(State::Sx, new_const_factor-const_factor);
SigSpec old_a = port(shift, \A), new_a; SigSpec old_a = port(shift, \A), new_a;
int trunc = 0; int trunc = 0;
@ -73,7 +80,7 @@ code
if (trunc > 0) if (trunc > 0)
new_a.remove(GetSize(new_a)-trunc, trunc); new_a.remove(GetSize(new_a)-trunc, trunc);
SigSpec new_b = {port(mul, const_factor_port == \A ? \B : \A), SigSpec(State::S0, new_const_factor_log2)}; SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
if (param(shift, \B_SIGNED).as_bool()) if (param(shift, \B_SIGNED).as_bool())
new_b.append(State::S0); new_b.append(State::S0);

4
tests/simple/peepopt.v
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@ -2,6 +2,10 @@ module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, in
assign o = i[s*W+:W]; assign o = i[s*W+:W];
endmodule endmodule
module peepopt_shiftmul_1 (output y, input [2:0] w);
assign y = 1'b1 >> (w * (3'b110));
endmodule
module peepopt_muldiv_0(input [1:0] i, output [1:0] o); module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
wire [3:0] t; wire [3:0] t;
assign t = i * 3; assign t = i * 3;