riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Do not access beyond bounds

This commit is contained in:
Eddie Hung 2019-07-19 13:58:50 -07:00
parent 54708dfbd7
commit cb0fd05215
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/opt/wreduce.cc
View File

@ -372,7 +372,7 @@ struct WreduceWorker
int i; int i;
for (i = 0; i < GetSize(sig); i++) { for (i = 0; i < GetSize(sig); i++) {
if (B[i] != S0 && (sub || A[i] != S0)) if (B.at(i, Sx) != S0 && (sub || A.at(i, Sx) != S0))
break; break;
if (B[i] == S0) if (B[i] == S0)
module->connect(sig[i], A[i]); module->connect(sig[i], A[i]);