From cac1bc6fbe4db01060bfd04a51c9e12f82ef6167 Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 25 May 2023 17:48:48 +0100 Subject: [PATCH] intel_alm: enable M10K initialisation --- techlibs/intel_alm/common/bram_m10k.txt | 2 +- techlibs/intel_alm/common/bram_m10k_map.v | 6 ++++-- techlibs/intel_alm/common/mem_sim.v | 8 +++++--- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/techlibs/intel_alm/common/bram_m10k.txt b/techlibs/intel_alm/common/bram_m10k.txt index 560711b65..60ebc5bf1 100644 --- a/techlibs/intel_alm/common/bram_m10k.txt +++ b/techlibs/intel_alm/common/bram_m10k.txt @@ -1,5 +1,5 @@ bram $__MISTRAL_M10K - init 0 # TODO: Re-enable when I figure out how BRAM init works + init 1 abits 13 @D8192x1 dbits 1 @D8192x1 abits 12 @D4096x2 diff --git a/techlibs/intel_alm/common/bram_m10k_map.v b/techlibs/intel_alm/common/bram_m10k_map.v index 8f9d4a3b3..3121b9d04 100644 --- a/techlibs/intel_alm/common/bram_m10k_map.v +++ b/techlibs/intel_alm/common/bram_m10k_map.v @@ -2,6 +2,8 @@ module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); +parameter INIT = 0; + parameter CFG_ABITS = 10; parameter CFG_DBITS = 10; @@ -11,6 +13,6 @@ input [CFG_DBITS-1:0] A1DATA; input A1EN, B1EN; output reg [CFG_DBITS-1:0] B1DATA; -MISTRAL_M10K #(.CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN)); +MISTRAL_M10K #(.INIT(INIT), .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN)); -endmodule \ No newline at end of file +endmodule diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v index c9ba8c7f1..563f1d241 100644 --- a/techlibs/intel_alm/common/mem_sim.v +++ b/techlibs/intel_alm/common/mem_sim.v @@ -3,7 +3,7 @@ // In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic // Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain // Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise -// the memory the ALM uses to store the look-up table data for general usage, +// the memory the ALM uses to store the look-up table data for general usage, // producing a 32 address by 20-bit block of memory. MLABs are spread out // around the chip, so they can be placed near where they are needed, rather than // being comparatively limited in placement for a deep but narrow memory such as @@ -43,7 +43,7 @@ // Quartus will pack external flops into the MLAB, but this is an assumption // that needs testing. -// The vendor sim model outputs 'x for a very short period (a few +// The vendor sim model outputs 'x for a very short period (a few // combinational delta cycles) after each write. This has been omitted from // the following model because it's very difficult to trigger this in practice // as clock cycles will be much longer than any potential blip of 'x, so the @@ -110,6 +110,8 @@ endmodule module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); +parameter INIT = 0; + parameter CFG_ABITS = 10; parameter CFG_DBITS = 10; @@ -119,7 +121,7 @@ input [CFG_DBITS-1:0] A1DATA; input A1EN, B1EN; output reg [CFG_DBITS-1:0] B1DATA; -reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0; +reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = INIT; `ifdef cyclonev specify