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Merge pull request #2010 from YosysHQ/claire/fixopt 

Fix "opt_expr -fine" bug introduced in 213a89558
This commit is contained in:
Claire Wolf 2020-05-02 11:20:02 +02:00 committed by GitHub
parent bbde241942 7f9ecddb7f
commit ca3fc3c882
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2 changed files with 29 additions and 7 deletions
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26
passes/opt/opt_expr.cc
View File

@ -682,25 +682,37 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_y = cell->getPort(ID::Y); RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
bool sub = cell->type == ID($sub); bool sub = cell->type == ID($sub);
int minsz = GetSize(sig_y);
minsz = std::min(minsz, GetSize(sig_a));
minsz = std::min(minsz, GetSize(sig_b));
int i; int i;
for (i = 0; i < GetSize(sig_y); i++) { for (i = 0; i < minsz; i++) {
RTLIL::SigBit b = sig_b.at(i, State::Sx); RTLIL::SigBit b = sig_b[i];
RTLIL::SigBit a = sig_a.at(i, State::Sx); RTLIL::SigBit a = sig_a[i];
if (b == State::S0 && a != State::Sx) if (b == State::S0)
module->connect(sig_y[i], a); module->connect(sig_y[i], a);
else if (sub && b == State::S1 && a == State::S1) else if (sub && b == State::S1 && a == State::S1)
module->connect(sig_y[i], State::S0); module->connect(sig_y[i], State::S0);
else if (!sub && a == State::S0 && b != State::Sx) else if (!sub && a == State::S0)
module->connect(sig_y[i], b); module->connect(sig_y[i], b);
else else
break; break;
} }
if (i > 0) { if (i > 0) {
cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
cell->setPort(ID::A, sig_a.extract_end(i)); log_debug("Stripping %d LSB bits of %s cell %s in module %s.\n", i, log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::B, sig_b.extract_end(i)); SigSpec new_a = sig_a.extract_end(i);
SigSpec new_b = sig_b.extract_end(i);
if (new_a.empty() && is_signed)
new_a = sig_a[i-1];
if (new_b.empty() && is_signed)
new_b = sig_b[i-1];
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
cell->setPort(ID::Y, sig_y.extract_end(i)); cell->setPort(ID::Y, sig_y.extract_end(i));
cell->fixup_parameters(); cell->fixup_parameters();
did_something = true; did_something = true;

10
tests/opt/bug2010.ys Normal file
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@ -0,0 +1,10 @@
read_verilog <<EOT
module test (
input signed [1:0] n,
output [3:0] dout
);
assign dout = n + 4'sd 4;
endmodule
EOT
equiv_opt -assert opt -fine