mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4184 from povik/check-loop-edges
Use cell edges data in `check`, improve messages
This commit is contained in:
N. Engelhardt
GitHub
commit
c98cdc2a42
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@ -307,6 +307,87 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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}
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}
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void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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log_assert(cell->type == ID($mem_v2));
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Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE);
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int n_rd_ports = cell->getParam(ID::RD_PORTS).as_int();
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int abits = cell->getParam(ID::ABITS).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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for (int i = 0; i < n_rd_ports; i++) {
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if (rd_clk_enable[i] != State::S0) {
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::RD_ARST, i, ID::RD_DATA, i * width + k, -1);
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continue;
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}
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for (int j = 0; j < abits; j++)
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::RD_ADDR, i * abits + j,
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ID::RD_DATA, i * width + k, -1);
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}
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}
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void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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log_assert(cell->type.in(ID($memrd), ID($memrd_v2)));
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int abits = cell->getParam(ID::ABITS).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
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if (cell->type == ID($memrd_v2)) {
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ARST, 0, ID::DATA, k, -1);
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}
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return;
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}
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for (int j = 0; j < abits; j++)
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ADDR, j, ID::DATA, k, -1);
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}
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void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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if (cell->type == ID($mem_v2))
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packed_mem_op(db, cell);
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else if (cell->type.in(ID($memrd), ID($memrd_v2)))
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memrd_op(db, cell);
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else if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit)))
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return; /* no edges here */
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else
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log_abort();
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}
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void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
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{
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int width = cell->getPort(ID::Q).size();
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if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
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for (int k = 0; k < width; k++) {
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db->add_edge(cell, ID::D, k, ID::Q, k, -1);
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db->add_edge(cell, ID::EN, 0, ID::Q, k, -1);
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}
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}
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if (cell->hasPort(ID::CLR))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::CLR, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::SET))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::SET, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::ALOAD))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ALOAD, 0, ID::Q, k, -1);
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if (cell->hasPort(ID::AD))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::AD, k, ID::Q, k, -1);
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if (cell->hasPort(ID::ARST))
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for (int k = 0; k < width; k++)
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db->add_edge(cell, ID::ARST, 0, ID::Q, k, -1);
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}
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PRIVATE_NAMESPACE_END
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bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
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@ -361,6 +442,18 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
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return true;
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}
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if (cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit))) {
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mem_op(this, cell);
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return true;
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}
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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ff_op(this, cell);
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return true;
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}
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// FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
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// FIXME: $lut $sop $alu $lcu $macc $fa
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// FIXME: $mul $div $mod $divfloor $modfloor $pow $slice $concat $bweqx
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// FIXME: $lut $sop $alu $lcu $macc $fa $logic_and $logic_or $bwmux
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@ -149,7 +149,7 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
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std::map<T, int, C> node_to_index;
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std::vector<std::set<int, IndirectCmp>> edges;
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std::vector<T> sorted;
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std::set<std::set<T, C>> loops;
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std::set<std::vector<T>> loops;
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TopoSort() : indirect_cmp(nodes)
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{
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@ -220,10 +220,10 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
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if (active_cells[root_index]) {
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found_loops = true;
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if (analyze_loops) {
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std::set<T, C> loop;
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std::vector<T> loop;
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for (int i = GetSize(active_stack) - 1; i >= 0; i--) {
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const int index = active_stack[i];
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loop.insert(nodes[index]);
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loop.push_back(nodes[index]);
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if (index == root_index)
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break;
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}
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@ -19,6 +19,7 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celledges.h"
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#include "kernel/celltypes.h"
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#include "kernel/utils.h"
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@ -102,10 +103,10 @@ struct CheckPass : public Pass {
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SigMap sigmap(module);
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dict<SigBit, vector<string>> wire_drivers;
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dict<SigBit, Cell *> driver_cells;
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dict<SigBit, int> wire_drivers_count;
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pool<SigBit> used_wires;
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TopoSort<string> topo;
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TopoSort<std::pair<RTLIL::IdString, int>> topo;
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for (auto &proc_it : module->processes)
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{
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std::vector<RTLIL::CaseRule*> all_cases = {&proc_it.second->root_case};
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@ -150,6 +151,50 @@ struct CheckPass : public Pass {
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}
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}
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struct CircuitEdgesDatabase : AbstractCellEdgesDatabase {
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TopoSort<std::pair<RTLIL::IdString, int>> &topo;
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SigMap sigmap;
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CircuitEdgesDatabase(TopoSort<std::pair<RTLIL::IdString, int>> &topo, SigMap &sigmap)
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: topo(topo), sigmap(sigmap) {}
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit,
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RTLIL::IdString to_port, int to_bit, int) override {
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SigSpec from_portsig = cell->getPort(from_port);
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SigSpec to_portsig = cell->getPort(to_port);
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log_assert(from_bit >= 0 && from_bit < from_portsig.size());
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log_assert(to_bit >= 0 && to_bit < to_portsig.size());
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SigBit from = sigmap(from_portsig[from_bit]);
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SigBit to = sigmap(to_portsig[to_bit]);
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if (from.wire && to.wire)
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topo.edge(std::make_pair(from.wire->name, from.offset), std::make_pair(to.wire->name, to.offset));
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}
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bool add_edges_from_cell(Cell *cell) {
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if (AbstractCellEdgesDatabase::add_edges_from_cell(cell))
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return true;
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// We don't have accurate cell edges, do the fallback of all input-output pairs
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for (auto &conn : cell->connections()) {
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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topo.edge(std::make_pair(bit.wire->name, bit.offset),
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std::make_pair(cell->name, -1));
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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if (bit.wire)
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topo.edge(std::make_pair(cell->name, -1),
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std::make_pair(bit.wire->name, bit.offset));
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}
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return true;
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}
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};
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CircuitEdgesDatabase edges_db(topo, sigmap);
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for (auto cell : module->cells())
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{
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if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
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@ -158,31 +203,30 @@ struct CheckPass : public Pass {
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counter++;
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cell_allowed:;
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}
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for (auto &conn : cell->connections()) {
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SigSpec sig = sigmap(conn.second);
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bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
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if (cell->input(conn.first))
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for (auto bit : sig)
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if (bit.wire) {
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if (logic_cell)
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topo.edge(stringf("wire %s", log_signal(bit)),
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stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
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used_wires.insert(bit);
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}
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if (cell->output(conn.first))
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for (int i = 0; i < GetSize(sig); i++) {
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if (logic_cell)
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topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
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stringf("wire %s", log_signal(sig[i])));
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if (sig[i].wire || !cell->input(conn.first))
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wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
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log_id(conn.first), i, log_id(cell), log_id(cell->type)));
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for (auto &conn : cell->connections()) {
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bool input = cell->input(conn.first);
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bool output = cell->output(conn.first);
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SigSpec sig = sigmap(conn.second);
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for (int i = 0; i < sig.size(); i++) {
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SigBit bit = sig[i];
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if (input && bit.wire)
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used_wires.insert(bit);
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if (output && !input && bit.wire)
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wire_drivers_count[bit]++;
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if (output && (bit.wire || !input))
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wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", log_id(conn.first), i,
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log_id(cell), log_id(cell->type)));
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if (output)
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driver_cells[bit] = cell;
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}
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if (!cell->input(conn.first) && cell->output(conn.first))
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for (auto bit : sig)
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if (bit.wire) wire_drivers_count[bit]++;
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}
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if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
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|| RTLIL::builtin_ff_cell_types().count(cell->type))
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edges_db.add_edges_from_cell(cell);
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}
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pool<SigBit> init_bits;
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@ -239,8 +283,72 @@ struct CheckPass : public Pass {
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topo.sort();
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for (auto &loop : topo.loops) {
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string message = stringf("found logic loop in module %s:\n", log_id(module));
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for (auto &str : loop)
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message += stringf(" %s\n", str.c_str());
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// `loop` only contains wire bits, or an occassional special helper node for cells for
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// which we have done the edges fallback. The cell and its ports that led to an edge is
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// an information we need to recover now. For that we need to have the previous wire bit
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// of the loop at hand.
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SigBit prev;
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for (auto it = loop.rbegin(); it != loop.rend(); it++)
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if (it->second != -1) { // skip the fallback helper nodes
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prev = SigBit(module->wire(it->first), it->second);
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break;
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}
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log_assert(prev != SigBit());
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for (auto &pair : loop) {
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if (pair.second == -1)
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continue; // helper node for edges fallback, we can ignore it
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struct MatchingEdgePrinter : AbstractCellEdgesDatabase {
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std::string &message;
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SigMap &sigmap;
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SigBit from, to;
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int nhits;
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const int HITS_LIMIT = 3;
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MatchingEdgePrinter(std::string &message, SigMap &sigmap, SigBit from, SigBit to)
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: message(message), sigmap(sigmap), from(from), to(to), nhits(0) {}
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void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit,
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RTLIL::IdString to_port, int to_bit, int) override {
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SigBit edge_from = sigmap(cell->getPort(from_port))[from_bit];
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SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit];
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if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT)
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message += stringf(" %s[%d] --> %s[%d]\n", log_id(from_port), from_bit,
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log_id(to_port), to_bit);
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if (nhits == HITS_LIMIT)
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message += " ...\n";
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}
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};
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Wire *wire = module->wire(pair.first);
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log_assert(wire);
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SigBit bit(module->wire(pair.first), pair.second);
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log_assert(driver_cells.count(bit));
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Cell *driver = driver_cells.at(bit);
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std::string driver_src;
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if (driver->has_attribute(ID::src)) {
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std::string src_attr = driver->get_src_attribute();
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driver_src = stringf(" source: %s", src_attr.c_str());
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}
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message += stringf(" cell %s (%s)%s\n", log_id(driver), log_id(driver->type), driver_src.c_str());
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MatchingEdgePrinter printer(message, sigmap, prev, bit);
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printer.add_edges_from_cell(driver);
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if (wire->name.isPublic()) {
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std::string wire_src;
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if (wire->has_attribute(ID::src)) {
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std::string src_attr = wire->get_src_attribute();
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wire_src = stringf(" source: %s", src_attr.c_str());
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}
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message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src.c_str());
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}
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prev = bit;
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}
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log_warning("%s", message.c_str());
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counter++;
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}
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@ -7,7 +7,7 @@ module top(...);
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input CLK;
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input EN;
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(* init = 24'h555555 *)
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output [19:0] Q;
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output [17:0] Q;
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input SRST;
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input ARST;
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input [1:0] CLR;
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@ -23,26 +23,20 @@ $sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_V
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$dffsr #(.CLK_POLARITY(1'b1), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff7 (.CLK(CLK), .SET(SET), .CLR(CLR), .D(Q[15:14]), .Q(Q[15:14]));
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$dffsre #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff8 (.CLK(CLK), .EN(EN), .SET(SET), .CLR(CLR), .D(Q[17:16]), .Q(Q[17:16]));
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$dlatch #(.EN_POLARITY(1'b1), .WIDTH(2)) ff9 (.EN(EN), .D(Q[19:18]), .Q(Q[19:18]));
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$adlatch #(.EN_POLARITY(1'b0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2), .WIDTH(2)) ff10 (.EN(EN), .ARST(ARST), .D(Q[21:20]), .Q(Q[21:20]));
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$dlatchsr #(.EN_POLARITY(1'b0), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0), .WIDTH(2)) ff11 (.EN(EN), .SET(SET), .CLR(CLR), .D(Q[23:22]), .Q(Q[23:22]));
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endmodule
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EOT
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design -save orig
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# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
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delete top/ff10 top/ff11
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load orig
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opt_dff -keepdc
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select -assert-count 1 t:$and
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select -assert-count 3 t:$dffe
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select -assert-count 3 t:$dlatch
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select -assert-count 3 t:$sr
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select -assert-count 2 t:$dlatch
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select -assert-count 2 t:$sr
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select -assert-none t:$and t:$dffe t:$dlatch t:$sr %% %n t:* %i
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design -load orig
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@ -50,7 +44,7 @@ simplemap
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opt_dff -keepdc
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select -assert-count 2 t:$_AND_
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select -assert-count 6 t:$_DFFE_??_
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select -assert-count 6 t:$_DLATCH_?_
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select -assert-count 6 t:$_SR_??_
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select -assert-count 4 t:$_DLATCH_?_
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select -assert-count 4 t:$_SR_??_
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select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i
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@ -0,0 +1,43 @@
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design -reset
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read -vlog2k <<EOF
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module top(input clk, input a, input b, output [9:0] x);
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wire [9:0] ripple;
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reg [9:0] prev_ripple = 9'b0;
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always @(posedge clk) prev_ripple <= ripple;
|
||||
assign ripple = {ripple[8:0], a} ^ prev_ripple; // only cyclic at the coarse-grain level
|
||||
assign x = ripple[9] + b;
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
prep
|
||||
check -assert
|
||||
|
||||
design -reset
|
||||
read -vlog2k <<EOF
|
||||
module top(clk, y, sideread_addr, sideread_data);
|
||||
input wire clk;
|
||||
|
||||
reg [7:0] mem [255:0];
|
||||
reg [8:0] i;
|
||||
initial begin
|
||||
for (i = 0; i < 256; i = i + 1)
|
||||
mem[i] = i * 371;
|
||||
end
|
||||
|
||||
output reg [7:0] y = 1;
|
||||
always @(posedge clk)
|
||||
y <= mem[y];
|
||||
|
||||
input wire [7:0] sideread_addr;
|
||||
output wire [7:0] sideread_data;
|
||||
assign sideread_data = mem[sideread_addr];
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
prep -rdff
|
||||
select -assert-count 1 t:$mem_v2
|
||||
check -assert
|
||||
memory_unpack
|
||||
select -assert-count 2 t:$memrd_v2
|
||||
check -assert
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# just so slightly adjust the example from check.ys to induce a loop
|
||||
design -reset
|
||||
read -vlog2k <<EOF
|
||||
module top(input clk, input a, input b, output [9:0] x);
|
||||
wire [9:0] ripple;
|
||||
reg [9:0] prev_ripple = 9'b0;
|
||||
|
||||
always @(posedge clk) prev_ripple <= ripple;
|
||||
assign ripple = {ripple[8:1], a, ripple[0]} ^ prev_ripple;
|
||||
assign x = ripple[9] + b;
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
prep
|
||||
logger -expect warning "found logic loop in module top:" 1
|
||||
logger -expect error "Found 1 problems in 'check -assert'" 1
|
||||
check -assert
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
# loop involving asynchronous memory ports
|
||||
design -reset
|
||||
read -vlog2k <<EOF
|
||||
module pingpong(input wire [1:0] x, output wire [3:0] y1, output wire [3:0] y2);
|
||||
reg [3:0] mem [15:0];
|
||||
reg [5:0] i;
|
||||
initial begin
|
||||
for (i = 0; i < 16; i = i + 1)
|
||||
mem[i] = i * 371;
|
||||
end
|
||||
|
||||
assign y1 = mem[{y2[3:2], x}];
|
||||
assign y2 = mem[y1];
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top pingpong
|
||||
prep
|
||||
logger -nowarn "found logic loop in module pingpong:"
|
||||
logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
|
||||
check -assert
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
# loop involving the asynchronous reset on a memory port
|
||||
design -reset
|
||||
read -vlog2k <<EOF
|
||||
module top(input wire clk, input wire [3:0] addr, output reg [3:0] data);
|
||||
reg [3:0] mem [15:0];
|
||||
reg [5:0] i;
|
||||
initial begin
|
||||
for (i = 0; i < 16; i = i + 1)
|
||||
mem[i] = i * 371;
|
||||
end
|
||||
|
||||
wire arst = !data[0];
|
||||
|
||||
always @(posedge arst, posedge clk) begin
|
||||
if (arst)
|
||||
data <= 4'hx;
|
||||
else
|
||||
data <= mem[addr];
|
||||
end
|
||||
endmodule
|
||||
EOF
|
||||
hierarchy -top top
|
||||
proc
|
||||
opt -keepdc
|
||||
memory_dff
|
||||
opt_clean
|
||||
logger -nowarn "found logic loop in module pingpong:"
|
||||
logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
|
||||
check -assert
|
||||
Loading…
Reference in New Issue