riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Accept disable case for SVA liveness properties.

This commit is contained in:
Diego H 2021-02-04 15:35:35 -06:00
parent baf1875307
commit c96eb2fbd7
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
frontends/verific/verificsva.cc
View File

@ -1759,6 +1759,11 @@ struct VerificSvaImporter
clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0); clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
} }
// accept in disable case
if (clocking.disable_sig != State::S0)
sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig);
// generate fair/live cell // generate fair/live cell
RTLIL::Cell *c = nullptr; RTLIL::Cell *c = nullptr;