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More $eq/$ne/$eqx/$nex fixes in opt_const

This commit is contained in:
Clifford Wolf 2013-12-27 15:10:07 +01:00
parent 72026a934e
commit c9699fe76d
1 changed files with 8 additions and 1 deletions
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9
passes/opt/opt_const.cc
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@ -160,6 +160,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
assert(a.chunks.size() == b.chunks.size()); assert(a.chunks.size() == b.chunks.size());
for (size_t i = 0; i < a.chunks.size(); i++) { for (size_t i = 0; i < a.chunks.size(); i++) {
if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL &&
a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0]) {
RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1);
new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
replace_cell(module, cell, "empty", "\\Y", new_y);
goto next_cell;
}
if (cell->type == "$eq" || cell->type == "$ne") { if (cell->type == "$eq" || cell->type == "$ne") {
if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1) if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
continue; continue;
@ -173,7 +180,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
if (new_a.width == 0) { if (new_a.width == 0) {
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0);
new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
replace_cell(module, cell, "empty", "\\Y", new_y); replace_cell(module, cell, "empty", "\\Y", new_y);
goto next_cell; goto next_cell;