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CMake: more generated files

This commit is contained in:
Miodrag Milanovic 2025-02-14 11:12:33 +01:00
parent d7f710abe0
commit c87bf56efb
2 changed files with 29 additions and 3 deletions
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16
techlibs/gatemate/CMakeLists.txt
View File

@ -5,6 +5,19 @@ target_sources(yosys_techlibs_gatemate INTERFACE
gatemate_foldinv.cc
)
add_custom_command(
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/make_lut_tree_lib.py
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/make_lut_tree_lib.py
OUTPUT lut_tree_cells.genlib lut_tree_map.v
COMMENT "Generating techlibs/gatemate/lut_tree_map.v..."
WORKING_DIRECTORY ${CMAKE_BINARY_DIR}
)
target_sources(yosys_techlibs_gatemate PRIVATE
${CMAKE_CURRENT_BINARY_DIR}/lut_tree_cells.genlib
${CMAKE_CURRENT_BINARY_DIR}/lut_tree_map.v
)
target_link_libraries(yosys PRIVATE yosys_techlibs_gatemate)
add_share_file("share/gatemate" "reg_map.v")
@ -19,3 +32,6 @@ add_share_file("share/gatemate" "brams.txt")
add_share_file("share/gatemate" "brams_init_20.vh")
add_share_file("share/gatemate" "brams_init_40.vh")
add_share_file("share/gatemate" "inv_map.v")
add_gen_share_file("share/gatemate" ${CMAKE_CURRENT_BINARY_DIR}/lut_tree_cells.genlib)
add_gen_share_file("share/gatemate" ${CMAKE_CURRENT_BINARY_DIR}/lut_tree_map.v)

16
techlibs/quicklogic/CMakeLists.txt
View File

@ -20,11 +20,21 @@ target_sources(yosys_techlibs_quicklogic INTERFACE
ql_dsp_macc.cc
)
target_sources(yosys_techlibs_quicklogic PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/ql_dsp_macc_pm.h)
add_custom_command(
COMMAND ${CMAKE_COMMAND} -E make_directory ${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/generate_bram_types_sim.py ${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f/bram_types_sim.v
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/generate_bram_types_sim.py
OUTPUT qlf_k6n10f/bram_types_sim.v
COMMENT "Generating techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v..."
)
target_sources(yosys_techlibs_quicklogic PRIVATE
${CMAKE_CURRENT_BINARY_DIR}/ql_dsp_macc_pm.h
${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f/bram_types_sim.v
)
target_link_libraries(yosys PRIVATE yosys_techlibs_quicklogic)
add_share_file("share/quicklogic/common" "common/cells_sim.v")
add_share_file("share/quicklogic/pp3" "pp3/ffs_map.v")
add_share_file("share/quicklogic/pp3" "pp3/lut_map.v")
@ -39,7 +49,7 @@ add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/libmap_brams.txt")
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/libmap_brams_map.v")
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/brams_map.v")
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/brams_sim.v")
#$(eval $(call add_gen_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v))
add_gen_share_file("share/quicklogic/qlf_k6n10f" "${CMAKE_CURRENT_BINARY_DIR}/qlf_k6n10f/bram_types_sim.v")
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/cells_sim.v")
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/ffs_map.v")
add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/dsp_sim.v")