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Fix typo and comments

This commit is contained in:
Eddie Hung 2019-07-09 10:38:07 -07:00
parent c91cb73562
commit c864995343
1 changed files with 4 additions and 4 deletions
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8
techlibs/xilinx/cells_map.v
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@ -204,7 +204,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
end end
else if (A_WIDTH <= 4) begin else if (A_WIDTH <= 4) begin
// Rather than extend with 1'bx which gets flattened to 1'b0 // Rather than extend with 1'bx which gets flattened to 1'b0
// causing the "don't care" status to get lost, extend with MSB // causing the "don't care" status to get lost, extend with MSBs
// so that we can recognise again later when mapping MUXF78 // so that we can recognise again later when mapping MUXF78
wire [4-1:0] Ax; wire [4-1:0] Ax;
if (A_WIDTH == 4) if (A_WIDTH == 4)
@ -215,7 +215,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
end end
else if (A_WIDTH <= 8) begin else if (A_WIDTH <= 8) begin
// Rather than extend with 1'bx which gets flattened to 1'b0 // Rather than extend with 1'bx which gets flattened to 1'b0
// causing the "don't care" status to get lost, extend with MSB // causing the "don't care" status to get lost, extend with MSBs
// so that we can recognise again later when mapping MUXF78 // so that we can recognise again later when mapping MUXF78
wire [8-1:0] Ax; wire [8-1:0] Ax;
if (A_WIDTH == 8) if (A_WIDTH == 8)
@ -230,13 +230,13 @@ module \$__XILINX_SHIFTX (A, B, Y);
end end
else if (A_WIDTH <= 16) begin else if (A_WIDTH <= 16) begin
// Rather than extend with 1'bx which gets flattened to 1'b0 // Rather than extend with 1'bx which gets flattened to 1'b0
// causing the "don't care" status to get lost, extend with MSB // causing the "don't care" status to get lost, extend with MSBs
// so that we can recognise again later when mapping MUXF78 // so that we can recognise again later when mapping MUXF78
wire [16-1:0] Ax; wire [16-1:0] Ax;
if (A_WIDTH == 16) if (A_WIDTH == 16)
assign Ax = A; assign Ax = A;
else else
assign Ax = {A[7-:8-A_WIDTH], A}; assign Ax = {A[7-:16-A_WIDTH], A};
wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4] wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
: B[3] ? Ax[ 8] : Ax[0]; : B[3] ? Ax[ 8] : Ax[0];
wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5] wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]