mirror of https://github.com/YosysHQ/yosys.git
Bugfix in hierarchy handling of blackbox module ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
parent
fefb652d56
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c80315cea4
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@ -1067,7 +1067,7 @@ AstModule::~AstModule()
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}
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}
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// create a new parametric module (when needed) and return the name of the generated module
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// create a new parametric module (when needed) and return the name of the generated module
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters)
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool)
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{
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{
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std::string stripped_name = name.str();
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std::string stripped_name = name.str();
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@ -283,7 +283,7 @@ namespace AST
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AstNode *ast;
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AstNode *ast;
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bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
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bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
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virtual ~AstModule();
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virtual ~AstModule();
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virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters);
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virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail);
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virtual RTLIL::Module *clone() const;
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virtual RTLIL::Module *clone() const;
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};
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};
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@ -639,8 +639,10 @@ RTLIL::Module::~Module()
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delete it->second;
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delete it->second;
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}
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}
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RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>)
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RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
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{
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{
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if (mayfail)
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return RTLIL::IdString();
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log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
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log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
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}
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}
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@ -906,7 +906,7 @@ public:
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Module();
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Module();
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virtual ~Module();
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virtual ~Module();
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virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters);
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virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false);
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virtual size_t count_id(RTLIL::IdString id);
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virtual size_t count_id(RTLIL::IdString id);
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virtual void sort();
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virtual void sort();
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@ -625,16 +625,15 @@ struct HierarchyPass : public Pass {
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for (auto module : design->modules())
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for (auto module : design->modules())
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for (auto cell : module->cells())
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for (auto cell : module->cells())
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{
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{
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if (GetSize(cell->parameters) != 0)
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continue;
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Module *m = design->module(cell->type);
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Module *m = design->module(cell->type);
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if (m == nullptr)
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if (m == nullptr)
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continue;
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continue;
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if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) {
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if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty()) {
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IdString new_m_name = m->derive(design, cell->parameters);
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IdString new_m_name = m->derive(design, cell->parameters, true);
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if (new_m_name.empty())
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continue;
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if (new_m_name != m->name) {
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if (new_m_name != m->name) {
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m = design->module(new_m_name);
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m = design->module(new_m_name);
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blackbox_derivatives.insert(m);
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blackbox_derivatives.insert(m);
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