Bugfix in hierarchy handling of blackbox module ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-01-05 13:28:45 +01:00
parent fefb652d56
commit c80315cea4
5 changed files with 10 additions and 9 deletions

View File

@ -1067,7 +1067,7 @@ AstModule::~AstModule()
} }
// create a new parametric module (when needed) and return the name of the generated module // create a new parametric module (when needed) and return the name of the generated module
RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters) RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool)
{ {
std::string stripped_name = name.str(); std::string stripped_name = name.str();

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@ -283,7 +283,7 @@ namespace AST
AstNode *ast; AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
virtual ~AstModule(); virtual ~AstModule();
virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters); virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail);
virtual RTLIL::Module *clone() const; virtual RTLIL::Module *clone() const;
}; };

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@ -639,8 +639,10 @@ RTLIL::Module::~Module()
delete it->second; delete it->second;
} }
RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>) RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
{ {
if (mayfail)
return RTLIL::IdString();
log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name)); log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
} }

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@ -906,7 +906,7 @@ public:
Module(); Module();
virtual ~Module(); virtual ~Module();
virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters); virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false);
virtual size_t count_id(RTLIL::IdString id); virtual size_t count_id(RTLIL::IdString id);
virtual void sort(); virtual void sort();

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@ -625,16 +625,15 @@ struct HierarchyPass : public Pass {
for (auto module : design->modules()) for (auto module : design->modules())
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (GetSize(cell->parameters) != 0)
continue;
Module *m = design->module(cell->type); Module *m = design->module(cell->type);
if (m == nullptr) if (m == nullptr)
continue; continue;
if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) { if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty()) {
IdString new_m_name = m->derive(design, cell->parameters); IdString new_m_name = m->derive(design, cell->parameters, true);
if (new_m_name.empty())
continue;
if (new_m_name != m->name) { if (new_m_name != m->name) {
m = design->module(new_m_name); m = design->module(new_m_name);
blackbox_derivatives.insert(m); blackbox_derivatives.insert(m);