diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 1a818a2ce..142d05d45 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -206,7 +206,9 @@ YOSYS_NAMESPACE_END
 "const"      { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
 "checker"    { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
 "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
+"final"      { SV_KEYWORD(TOK_FINAL); }
 "logic"      { SV_KEYWORD(TOK_LOGIC); }
+"var"        { SV_KEYWORD(TOK_VAR); }
 "bit"        { SV_KEYWORD(TOK_REG); }
 
 "eventually"   { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 351f38101..4914b2c18 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -125,11 +125,11 @@ struct specify_rise_fall {
 
 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
 %token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER
-%token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
+%token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
-%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT
+%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
@@ -482,6 +482,9 @@ wire_type_token:
 	TOK_LOGIC {
 		astbuf3->is_logic = true;
 	} |
+	TOK_VAR {
+		astbuf3->is_logic = true;
+	} |
 	TOK_INTEGER {
 		astbuf3->is_reg = true;
 		astbuf3->range_left = 31;
@@ -1614,6 +1617,9 @@ opt_property:
 	TOK_PROPERTY {
 		$$ = true;
 	} |
+	TOK_FINAL {
+		$$ = false;
+	} |
 	/* empty */ {
 		$$ = false;
 	};
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 2f7995071..c00ea06b2 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -242,6 +242,10 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		}
 	}
 
+	SigPool raw_used_signals_noaliases;
+	for (auto &it : module->connections_)
+		raw_used_signals_noaliases.add(it.second);
+
 	module->connections_.clear();
 
 	SigPool used_signals;
@@ -251,6 +255,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		for (auto &it2 : cell->connections_) {
 			assign_map.apply(it2.second);
 			used_signals.add(it2.second);
+			raw_used_signals_noaliases.add(it2.second);
 			if (!ct_all.cell_output(cell->type, it2.first))
 				used_signals_nodrivers.add(it2.second);
 		}
@@ -277,23 +282,30 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		SigSpec s1 = SigSpec(wire), s2 = assign_map(s1);
 		log_assert(GetSize(s1) == GetSize(s2));
 
+		Const initval;
+		if (wire->attributes.count("\\init"))
+			initval = wire->attributes.at("\\init");
+		if (GetSize(initval) != GetSize(wire))
+			initval.bits.resize(GetSize(wire), State::Sx);
+		if (initval.is_fully_undef())
+			wire->attributes.erase("\\init");
+
 		bool maybe_del = false;
-		if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep") || wire->attributes.count("\\init")) {
-			if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep"))
-				maybe_del = true;
+		if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) {
+			/* do not delete anything with "keep" or module ports or initialized wires */
+		} else
+		if (!purge_mode && check_public_name(wire->name)) {
+			/* do not get rid of public names unless in purge mode */
 		} else {
-			if (!used_signals.check_any(s2))
+			if (!raw_used_signals_noaliases.check_any(s1))
+				maybe_del = true;
+			if (!used_signals_nodrivers.check_any(s2))
 				maybe_del = true;
 		}
 
 		if (maybe_del) {
 			maybe_del_wires.push_back(wire);
 		} else {
-			Const initval;
-			if (wire->attributes.count("\\init"))
-				initval = wire->attributes.at("\\init");
-			if (GetSize(initval) != GetSize(wire))
-				initval.bits.resize(GetSize(wire), State::Sx);
 			RTLIL::SigSig new_conn;
 			for (int i = 0; i < GetSize(s1); i++)
 				if (s1[i] != s2[i]) {
@@ -341,7 +353,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 	int del_wires_count = 0;
 	for (auto wire : maybe_del_wires) {
 		SigSpec s1 = SigSpec(wire);
-		if (used_signals.check_any(s1)) {
+		if (used_signals_nodrivers.check_any(s1)) {
 			SigSpec s2 = assign_map(s1);
 			Const initval;
 			if (wire->attributes.count("\\init"))