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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig

This commit is contained in:
Eddie Hung 2019-04-12 17:09:24 -07:00
parent a16123cc7d acf3f5694b
commit c776db3320
1 changed files with 32 additions and 12 deletions
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44
frontends/aiger/aigerparse.cc
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@ -439,7 +439,7 @@ next_line:
std::string type, symbol; std::string type, symbol;
int variable, index; int variable, index;
while (mf >> type >> variable >> index >> symbol) { while (mf >> type >> variable >> index >> symbol) {
RTLIL::IdString escaped_symbol = RTLIL::escape_id(symbol); RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
if (type == "input") { if (type == "input") {
log_assert(static_cast<unsigned>(variable) < inputs.size()); log_assert(static_cast<unsigned>(variable) < inputs.size());
RTLIL::Wire* wire = inputs[variable]; RTLIL::Wire* wire = inputs[variable];
@ -450,21 +450,21 @@ next_line:
// Cope with the fact that a CI might be identical // Cope with the fact that a CI might be identical
// to a PI (necessary due to ABC); in those cases // to a PI (necessary due to ABC); in those cases
// simply connect the latter to the former // simply connect the latter to the former
RTLIL::Wire* existing = module->wire(escaped_symbol); RTLIL::Wire* existing = module->wire(escaped_s);
if (!existing) if (!existing)
module->rename(wire, escaped_symbol); module->rename(wire, escaped_s);
else { else {
wire->port_input = false; wire->port_input = false;
module->connect(wire, existing); module->connect(wire, existing);
} }
} }
else if (index > 0) { else if (index > 0) {
std::string indexed_name = stringf("%s[%d]", escaped_symbol.c_str(), index); std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
RTLIL::Wire* existing = module->wire(indexed_name); RTLIL::Wire* existing = module->wire(indexed_name);
if (!existing) { if (!existing) {
module->rename(wire, indexed_name); module->rename(wire, indexed_name);
if (wideports) if (wideports)
wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
} }
else { else {
module->connect(wire, existing); module->connect(wire, existing);
@ -482,21 +482,41 @@ next_line:
// Cope with the fact that a CO might be identical // Cope with the fact that a CO might be identical
// to a PO (necessary due to ABC); in those cases // to a PO (necessary due to ABC); in those cases
// simply connect the latter to the former // simply connect the latter to the former
RTLIL::Wire* existing = module->wire(escaped_symbol); RTLIL::Wire* existing = module->wire(escaped_s);
if (!existing) if (!existing) {
module->rename(wire, escaped_symbol); if (escaped_s.ends_with("$inout.out")) {
wire->port_output = false;
RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
log_assert(in_wire);
log_assert(in_wire->port_input && !in_wire->port_output);
in_wire->port_output = true;
module->connect(in_wire, wire);
}
else
module->rename(wire, escaped_s);
}
else { else {
wire->port_output = false; wire->port_output = false;
module->connect(wire, existing); module->connect(wire, existing);
} }
} }
else if (index > 0) { else if (index > 0) {
std::string indexed_name = stringf("%s[%d]", escaped_symbol.c_str(), index); std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
RTLIL::Wire* existing = module->wire(indexed_name); RTLIL::Wire* existing = module->wire(indexed_name);
if (!existing) { if (!existing) {
module->rename(wire, indexed_name); if (escaped_s.ends_with("$inout.out")) {
if (wideports) wire->port_output = false;
wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
log_assert(in_wire);
log_assert(in_wire->port_input && !in_wire->port_output);
in_wire->port_output = true;
module->connect(in_wire, wire);
}
else {
module->rename(wire, indexed_name);
if (wideports)
wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
}
} }
else { else {
module->connect(wire, existing); module->connect(wire, existing);