riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Missing endmodule

This commit is contained in:
Eddie Hung 2019-11-22 12:37:57 -08:00
parent 0ab1e496dc
commit c761fa49b7
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
tests/simple_abc9/abc9.v
View File

@ -288,3 +288,4 @@ endmodule
module abc9_test033(input clk, d, output reg q1, q2); module abc9_test033(input clk, d, output reg q1, q2);
always @(posedge clk) q1 <= d; always @(posedge clk) q1 <= d;
always @(posedge clk) q2 <= q1; always @(posedge clk) q2 <= q1;
endmodule