mirror of https://github.com/YosysHQ/yosys.git
Cleanup
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@ -83,7 +83,7 @@ struct XAigerWriter
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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dict<SigBit, std::pair<int, RTLIL::State>> ff_bits;
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dict<SigBit, std::pair<int,int>> ff_bits;
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dict<SigBit, float> arrival_times;
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vector<pair<int, int>> aig_gates;
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@ -245,7 +245,7 @@ struct XAigerWriter
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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alias_map[Q] = D;
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auto r = ff_bits.insert(std::make_pair(D, std::make_pair(0, State::Sx)));
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auto r = ff_bits.insert(std::make_pair(D, std::make_pair(0, 2)));
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log_assert(r.second);
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continue;
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}
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@ -369,10 +369,16 @@ struct XAigerWriter
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it = cell->attributes.find(ID(abc9_init));
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log_assert(it != cell->attributes.end());
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log_assert(GetSize(it->second) == 1);
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rhs.second = it->second[0];
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if (it->second[0] == State::S1)
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rhs.second = 1;
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else if (it->second[0] == State::S0)
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rhs.second = 0;
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else {
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log_assert(it->second[0] == State::Sx);
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rhs.second = 0;
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}
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cell->attributes.erase(it);
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auto arrival = r.first->second.second;
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if (arrival)
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arrival_times[d] = arrival;
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@ -815,13 +821,8 @@ struct XAigerWriter
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int mergeability = i.second.first;
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log_assert(mergeability > 0);
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write_r_buffer(mergeability);
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State init = i.second.second;
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if (init == State::S1)
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write_s_buffer(1);
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else if (init == State::S0)
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write_s_buffer(0);
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else
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write_s_buffer(0);
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int init = i.second.second;
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write_s_buffer(init);
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write_i_buffer(arrival_times.at(bit, 0));
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//write_o_buffer(0);
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}
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