mirror of https://github.com/YosysHQ/yosys.git
optbarriers: add command to add/remove optimization barriers
* This can optionally ignore rewriting the outputs of cells or processes * This by default rewrites drivers of wires with public names but can also optionally rewrite drivers of wires with private names * A -remove flag allows cleaning up the design by replacing barriers with connections
This commit is contained in:
George Rennie
parent
c352f71fc0
commit
c6e8fb2432
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@ -51,3 +51,4 @@ OBJS += passes/cmds/future.o
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OBJS += passes/cmds/box_derive.o
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OBJS += passes/cmds/example_dt.o
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OBJS += passes/cmds/portarcs.o
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OBJS += passes/cmds/optbarriers.o
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@ -0,0 +1,228 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 George Rennie <georgrennie@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Standard visitor helper
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template<class... Ts>
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struct overloaded : Ts... { using Ts::operator()...; };
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template<class... Ts>
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overloaded(Ts...) -> overloaded<Ts...>;
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struct OptBarriersPass : public Pass {
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OptBarriersPass() : Pass("optbarriers", "insert optimization barriers") {}
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void help() override {
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log("\n");
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log(" optbarriers [options] [selection]\n");
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log("\n");
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log("Insert optimization barriers to drivers of selected public wires.\n");
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log("\n");
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log("\n");
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log(" -nocells\n");
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log(" don't add optimization barriers to the outputs of cells\n");
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log("\n");
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log(" -noprocs\n");
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log(" don't add optimization barriers to the outputs of processes\n");
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log("\n");
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log(" -private\n");
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log(" also add optimization barriers to private wires\n");
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log("\n");
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log(" -remove\n");
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log(" replace selected optimization barriers with connections\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing OPTBARRIERS pass (insert optimization barriers).\n");
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bool nocells_mode = false;
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bool noprocs_mode = false;
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bool private_mode = false;
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bool remove_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-nocells") {
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nocells_mode = true;
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continue;
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}
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if (arg == "-noprocs") {
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noprocs_mode = true;
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continue;
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}
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if (arg == "-private") {
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private_mode = true;
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continue;
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}
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if (arg == "-remove") {
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remove_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (remove_mode) {
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log("Replacing optimization barriers with connections.\n");
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remove_barriers(design);
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return;
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}
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for (auto* module : design->selected_modules()) {
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// We can't just sigmap and iterate through wires for rewriting as
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// we want to maintain the structure in connections, and sigmap
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// will just return a canonical wire which does not have to be one
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// that is directly driving the wire. Therefore for each type of
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// object that could be driving the wires (cells, processes,
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// connections) we rewrite the sigspecs.
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// Keep track of which wires we have allocated new wires for
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dict<RTLIL::Wire*, RTLIL::Wire*> new_wires;
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// Keep track of bit pairs we need to construct barriers for from
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// Y to A
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dict<RTLIL::SigBit, RTLIL::SigBit> new_barriers;
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// Skip constants, unselected wires and private wires when not in
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// private mode. This works for SigChunk or SigBit input.
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const auto skip = [&](const auto& chunk) {
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if (!chunk.is_wire())
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return true;
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if (!design->selected(module, chunk.wire))
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return true;
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if (!private_mode && !chunk.wire->name.isPublic())
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return true;
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return false;
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};
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const auto rewrite_sigspec = [&](const SigSpec& sig) {
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RTLIL::SigSpec new_output;
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for (const auto& chunk : sig.chunks()) {
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if (skip(chunk)) {
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new_output.append(chunk);
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continue;
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}
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// Add a wire to drive if one does not already exist
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auto* new_wire = new_wires.at(chunk.wire, nullptr);
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if (!new_wire) {
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new_wire = module->addWire(NEW_ID, GetSize(chunk.wire));
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new_wires.emplace(chunk.wire, new_wire);
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}
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RTLIL::SigChunk new_chunk = chunk;
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new_chunk.wire = new_wire;
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// Rewrite output to drive new wire, and schedule adding
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// barrier bits from new wire to original
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new_output.append(new_chunk);
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for (int i = 0; i < GetSize(chunk); i++)
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new_barriers.emplace(chunk[i], new_chunk[i]);
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}
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return new_output;
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};
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// Rewrite cell outputs
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if (!nocells_mode)
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for (auto* cell : module->cells())
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if (cell->type != ID($barrier))
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for (const auto& [name, sig] : cell->connections())
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if (cell->output(name))
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cell->setPort(name, rewrite_sigspec(sig));
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// Rewrite connections in processes
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if (!noprocs_mode) {
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const auto proc_rewriter = overloaded{
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// Don't do anything for input sigspecs
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[&](const SigSpec&) {},
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// Rewrite connections to drive barrier if needed
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[&](SigSpec& lhs, const SigSpec&) {
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lhs = rewrite_sigspec(lhs);
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}
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};
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for (auto& proc : module->processes)
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proc.second->rewrite_sigspecs2(proc_rewriter);
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}
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// Add all the scheduled barriers. To minimize the number of cells,
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// first construct a sigspec of all bits, then sort and unify before
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// creating barriers
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SigSpec barrier_y;
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for (const auto&[y_bit, _] : new_barriers)
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barrier_y.append(y_bit);
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barrier_y.sort_and_unify();
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for (const auto& sig_y : barrier_y.chunks()) {
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log_assert(sig_y.is_wire());
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SigSpec sig_a;
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for (int i = 0; i < GetSize(sig_y); i++)
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sig_a.append(new_barriers[sig_y[i]]);
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module->addBarrier(NEW_ID, sig_a, sig_y);
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}
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// Rewrite connections
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std::vector<RTLIL::SigSig> new_connections;
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for (const auto& conn : module->connections()) {
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RTLIL::SigSig skip_conn, barrier_conn;
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for (int i = 0; i < GetSize(conn.first); i++) {
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auto& sigsig = skip(conn.first[i]) ? skip_conn : barrier_conn;
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sigsig.first.append(conn.first[i]);
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sigsig.second.append(conn.second[i]);
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}
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if (!skip_conn.first.empty())
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new_connections.emplace_back(std::move(skip_conn));
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if (!barrier_conn.first.empty())
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module->addBarrier(NEW_ID, barrier_conn.second, barrier_conn.first);
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}
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module->new_connections(new_connections);
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}
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}
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void remove_barriers(RTLIL::Design* design) {
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for (auto* module : design->selected_modules()) {
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std::vector<RTLIL::Cell*> barriers;
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for (auto* cell : module->selected_cells())
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if (cell->type == ID($barrier))
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barriers.emplace_back(cell);
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for (auto* cell : barriers) {
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const auto lhs = cell->getPort(ID::Y), rhs = cell->getPort(ID::A);
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module->connect(lhs, rhs);
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module->remove(cell);
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}
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}
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}
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} OptBarriersPass;
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PRIVATE_NAMESPACE_END
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