mirror of https://github.com/YosysHQ/yosys.git
parent
62c66406ad
commit
c6d15c9aad
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@ -32,8 +32,7 @@ struct EquivOptPass:public ScriptPass
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log("\n");
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log("\n");
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log(" equiv_opt [options] [command]\n");
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log(" equiv_opt [options] [command]\n");
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log("\n");
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log("\n");
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log("This command uses temporal induction to check circuit equivalence before and\n");
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log("This command checks circuit equivalence before and after an optimization pass.\n");
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log("after an optimization pass.\n");
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log("\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" only run the commands between the labels (see below). an empty\n");
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@ -157,7 +156,7 @@ struct EquivOptPass:public ScriptPass
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if (check_label("prove")) {
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if (check_label("prove")) {
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if (multiclock || help_mode)
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if (multiclock || help_mode)
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run("clk2fflogic", "(only with -multiclock)");
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run("clk2fflogic", "(only with -multiclock)");
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if (!multiclock || help_mode)
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else
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run("async2sync", "(only without -multiclock)");
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run("async2sync", "(only without -multiclock)");
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run("equiv_make gold gate equiv");
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run("equiv_make gold gate equiv");
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if (help_mode)
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if (help_mode)
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