From 83ffb23739ff09591fb81e0c7b3b289d9fc73fb7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 12 Mar 2018 13:52:35 +0100 Subject: [PATCH 001/184] Add "setundef -undef" Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 9827ac0b1..389c3790e 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -40,6 +40,9 @@ struct SetundefWorker if (next_bit_mode == 1) return RTLIL::State::S1; + if (next_bit_mode == 4) + return RTLIL::State::Sx; + // xorshift32 next_bit_state ^= next_bit_state << 13; next_bit_state ^= next_bit_state >> 17; @@ -81,6 +84,9 @@ struct SetundefPass : public Pass { log(" -one\n"); log(" replace with bits set (1)\n"); log("\n"); + log(" -undef\n"); + log(" replace with undef (x) bits, may be used with -undriven\n"); + log("\n"); log(" -anyseq\n"); log(" replace with $anyseq drivers (for formal)\n"); log("\n"); @@ -123,6 +129,11 @@ struct SetundefPass : public Pass { worker.next_bit_mode = 2; continue; } + if (args[argidx] == "-undef") { + got_value = true; + worker.next_bit_mode = 4; + continue; + } if (args[argidx] == "-init") { init_mode = true; continue; From 08225f49a410c7df6d7d6fe098a4dabc68789ac5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 12 Mar 2018 13:52:52 +0100 Subject: [PATCH 002/184] Add "expose -input" Signed-off-by: Clifford Wolf --- passes/sat/expose.cc | 53 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 44 insertions(+), 9 deletions(-) diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 9427547f3..fa8f0c6be 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -236,6 +236,10 @@ struct ExposePass : public Pass { log(" when exposing a wire, create an input/output pair and cut the internal\n"); log(" signal path at that wire.\n"); log("\n"); + log(" -input\n"); + log(" when exposing a wire, create an input port and disconnect the internal\n"); + log(" driver.\n"); + log("\n"); log(" -shared\n"); log(" only expose those signals that are shared among the selected modules.\n"); log(" this is useful for preparing modules for equivalence checking.\n"); @@ -259,6 +263,7 @@ struct ExposePass : public Pass { bool flag_evert = false; bool flag_dff = false; bool flag_cut = false; + bool flag_input = false; bool flag_evert_dff = false; std::string sep = "."; @@ -279,10 +284,14 @@ struct ExposePass : public Pass { flag_dff = true; continue; } - if (args[argidx] == "-cut") { + if (args[argidx] == "-cut" && !flag_input) { flag_cut = true; continue; } + if (args[argidx] == "-input" && !flag_cut) { + flag_input = true; + continue; + } if (args[argidx] == "-evert-dff") { flag_evert_dff = true; continue; @@ -464,16 +473,42 @@ struct ExposePass : public Pass { continue; } - if (!it.second->port_output) { - it.second->port_output = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name)); + if (flag_input) + { + if (!it.second->port_input) { + it.second->port_input = true; + log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name)); + RTLIL::Wire *w = module->addWire(NEW_ID, GetSize(it.second)); + out_to_in_map.add(it.second, w); + } + } + else + { + if (!it.second->port_output) { + it.second->port_output = true; + log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name)); + } + + if (flag_cut) { + RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width); + in_wire->port_input = true; + out_to_in_map.add(sigmap(it.second), in_wire); + } + } + } + + if (flag_input) + { + for (auto &it : module->cells_) { + if (!ct.cell_known(it.second->type)) + continue; + for (auto &conn : it.second->connections_) + if (ct.cell_output(it.second->type, conn.first)) + conn.second = out_to_in_map(sigmap(conn.second)); } - if (flag_cut) { - RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width); - in_wire->port_input = true; - out_to_in_map.add(sigmap(it.second), in_wire); - } + for (auto &conn : module->connections_) + conn.first = out_to_in_map(sigmap(conn.first)); } if (flag_cut) From bf402a806a4312cf29056d86872245be3a254fce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 14 Mar 2018 20:22:11 +0100 Subject: [PATCH 003/184] Fix handling of SV compilation units in Verific front-end Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 51 +++++++++++++++++------------------- 1 file changed, 24 insertions(+), 27 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 7b5dac309..b8c2e7181 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1536,6 +1536,10 @@ struct VerificPass : public Pass { log("\n"); log("Load the specified Verilog/SystemVerilog files into Verific.\n"); log("\n"); + log("All files specified in one call to this command are one compilation unit.\n"); + log("Files passed to different calls to this command are treated as belonging to\n"); + log("different compilation units.\n"); + log("\n"); log("\n"); log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} ..\n"); log("\n"); @@ -1662,38 +1666,31 @@ struct VerificPass : public Pass { goto check_error; } - if (GetSize(args) > argidx && args[argidx] == "-vlog95") { - for (argidx++; argidx < GetSize(args); argidx++) - if (!veri_file::Analyze(args[argidx].c_str(), veri_file::VERILOG_95)) - log_cmd_error("Reading `%s' in VERILOG_95 mode failed.\n", args[argidx].c_str()); - goto check_error; - } + if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" || + args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv")) + { + Array file_names; + unsigned verilog_mode; - if (GetSize(args) > argidx && args[argidx] == "-vlog2k") { - for (argidx++; argidx < GetSize(args); argidx++) - if (!veri_file::Analyze(args[argidx].c_str(), veri_file::VERILOG_2K)) - log_cmd_error("Reading `%s' in VERILOG_2K mode failed.\n", args[argidx].c_str()); - goto check_error; - } + if (args[argidx] == "-vlog95") + verilog_mode = veri_file::VERILOG_95; + else if (args[argidx] == "-vlog2k") + verilog_mode = veri_file::VERILOG_2K; + else if (args[argidx] == "-sv2005") + verilog_mode = veri_file::SYSTEM_VERILOG_2005; + else if (args[argidx] == "-sv2009") + verilog_mode = veri_file::SYSTEM_VERILOG_2009; + else if (args[argidx] == "-sv2012" || args[argidx] == "-sv") + verilog_mode = veri_file::SYSTEM_VERILOG; + else + log_abort(); - if (GetSize(args) > argidx && args[argidx] == "-sv2005") { for (argidx++; argidx < GetSize(args); argidx++) - if (!veri_file::Analyze(args[argidx].c_str(), veri_file::SYSTEM_VERILOG_2005)) - log_cmd_error("Reading `%s' in SYSTEM_VERILOG_2005 mode failed.\n", args[argidx].c_str()); - goto check_error; - } + file_names.Insert(args[argidx].c_str()); - if (GetSize(args) > argidx && args[argidx] == "-sv2009") { - for (argidx++; argidx < GetSize(args); argidx++) - if (!veri_file::Analyze(args[argidx].c_str(), veri_file::SYSTEM_VERILOG_2009)) - log_cmd_error("Reading `%s' in SYSTEM_VERILOG_2009 mode failed.\n", args[argidx].c_str()); - goto check_error; - } + if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU)) + log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); - if (GetSize(args) > argidx && (args[argidx] == "-sv2012" || args[argidx] == "-sv")) { - for (argidx++; argidx < GetSize(args); argidx++) - if (!veri_file::Analyze(args[argidx].c_str(), veri_file::SYSTEM_VERILOG)) - log_cmd_error("Reading `%s' in SYSTEM_VERILOG mode failed.\n", args[argidx].c_str()); goto check_error; } From 7cf9d8802832a12b46a32cebb039d161586f414f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 15 Mar 2018 18:20:37 +0100 Subject: [PATCH 004/184] Improve import of memories via Verific Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 39 +++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b8c2e7181..9f61d69a4 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1044,23 +1044,30 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == OPER_READ_PORT) { RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name())); - if (memory->width != int(inst->OutputSize())) - log_error("Import of asymetric memories from Verific is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); + int numchunks = int(inst->OutputSize()) / memory->width; + int chunksbits = ceil_log2(numchunks); - RTLIL::SigSpec addr = operatorInput1(inst); - RTLIL::SigSpec data = operatorOutput(inst); + if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0) + log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); - RTLIL::Cell *cell = module->addCell(inst_name, "$memrd"); - cell->parameters["\\MEMID"] = memory->name.str(); - cell->parameters["\\CLK_ENABLE"] = false; - cell->parameters["\\CLK_POLARITY"] = true; - cell->parameters["\\TRANSPARENT"] = false; - cell->parameters["\\ABITS"] = GetSize(addr); - cell->parameters["\\WIDTH"] = GetSize(data); - cell->setPort("\\CLK", RTLIL::State::Sx); - cell->setPort("\\EN", RTLIL::State::Sx); - cell->setPort("\\ADDR", addr); - cell->setPort("\\DATA", data); + for (int i = 0; i < numchunks; i++) + { + RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; + RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); + + RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : + RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memrd"); + cell->parameters["\\MEMID"] = memory->name.str(); + cell->parameters["\\CLK_ENABLE"] = false; + cell->parameters["\\CLK_POLARITY"] = true; + cell->parameters["\\TRANSPARENT"] = false; + cell->parameters["\\ABITS"] = GetSize(addr); + cell->parameters["\\WIDTH"] = GetSize(data); + cell->setPort("\\CLK", RTLIL::State::Sx); + cell->setPort("\\EN", RTLIL::State::Sx); + cell->setPort("\\ADDR", addr); + cell->setPort("\\DATA", data); + } continue; } @@ -1068,7 +1075,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se { RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name())); if (memory->width != int(inst->Input2Size())) - log_error("Import of asymetric memories from Verific is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); + log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); RTLIL::SigSpec addr = operatorInput1(inst); RTLIL::SigSpec data = operatorInput2(inst); From 462e9f7bd4e072bee5ac7a9552086db5dc09ae67 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 16 Mar 2018 12:15:36 +0100 Subject: [PATCH 005/184] Add todo for more features to verificsva.cc Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 53 ++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 8 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 5abe0eb35..c56854acc 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -21,14 +21,51 @@ // Currently supported SVA sequence and property syntax: // http://symbiyosys.readthedocs.io/en/latest/verific.html // -// Todos: -// property and property -// sequence |-> always sequence -// sequence |-> eventually sequence -// sequence implies sequence -// sequence iff sequence -// accept_on (expr) prop -// reject_on (expr) prop +// Next gen property syntax: +// basic_property +// [antecedent_condition] property +// [antecedent_condition] always.. property +// [antecedent_condition] eventually.. basic_property +// [antecedent_condition] property until.. expression +// [antecedent_condition] basic_property until.. basic_property +// +// antecedent_condition: +// sequence |-> +// sequence |=> +// +// basic_property: +// sequence +// sequence #-# basic_property +// sequence #=# basic_property +// basic_property or basic_property (cover only) +// basic_property and basic_property (assert/assume only) +// basic_property implies basic_property +// basic_property iff basic_property +// +// sequence: +// expression +// sequence ##N sequence +// sequence ##[*] sequence +// sequence ##[+] sequence +// sequence ##[N:M] sequence +// sequence ##[N:$] sequence +// sequence [*] +// sequence [+] +// sequence [*N] +// sequence [*N:M] +// sequence [*N:$] +// sequence or sequence +// sequence and sequence +// expression throughout sequence +// sequence intersect sequence +// sequence within sequence +// first_match( sequence ) +// expression [=N] +// expression [=N:M] +// expression [=N:$] +// expression [->N] +// expression [->N:M] +// expression [->N:$] #include "kernel/yosys.h" From 38596ce68f51b57ee0f1a51f2abc2b9d9011cf75 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 16 Mar 2018 12:16:52 +0100 Subject: [PATCH 006/184] Update todo for more features to verificsva.cc Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index c56854acc..f221dfcc2 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -35,6 +35,7 @@ // // basic_property: // sequence +// not basic_property // sequence #-# basic_property // sequence #=# basic_property // basic_property or basic_property (cover only) From e7862d4f644d4fc6a97e9c66da431f7a22a0ceef Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 16 Mar 2018 15:48:48 +0100 Subject: [PATCH 007/184] Update todo for more features to verificsva.cc Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index f221dfcc2..c9c341516 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -27,7 +27,7 @@ // [antecedent_condition] always.. property // [antecedent_condition] eventually.. basic_property // [antecedent_condition] property until.. expression -// [antecedent_condition] basic_property until.. basic_property +// [antecedent_condition] basic_property until.. basic_property (assert/assume only) // // antecedent_condition: // sequence |-> @@ -38,8 +38,8 @@ // not basic_property // sequence #-# basic_property // sequence #=# basic_property -// basic_property or basic_property (cover only) -// basic_property and basic_property (assert/assume only) +// basic_property or basic_property (cover only) +// basic_property and basic_property (assert/assume only) // basic_property implies basic_property // basic_property iff basic_property // From 4d4e3a8ca62dd9484942d3adf107354468f9897d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 17 Mar 2018 12:17:53 +0100 Subject: [PATCH 008/184] Improve handling of invalid check-sat result in smtio.py Signed-off-by: Clifford Wolf --- backends/smt2/smtio.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index 1d5c89d8e..5c46da4e7 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -646,12 +646,13 @@ class SmtIo: sys.stderr.flush() result = self.read() - assert result in ["sat", "unsat"] if self.debug_file: print("(set-info :status %s)" % result, file=self.debug_file) print("(check-sat)", file=self.debug_file) self.debug_file.flush() + + assert result in ["sat", "unsat"] return result def parse(self, stmt): From 3f0070247590458c5ed28c5a7abfc3b9d1ec138b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 17 Mar 2018 18:06:17 +0100 Subject: [PATCH 009/184] Improve yosys-smtbmc log output and error handling Signed-off-by: Clifford Wolf --- backends/smt2/smtio.py | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index 5c46da4e7..215b4a008 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -218,7 +218,7 @@ class SmtIo: def timestamp(self): secs = int(time() - self.start_time) - return "## %6d %3d:%02d:%02d " % (secs, secs // (60*60), (secs // 60) % 60, secs % 60) + return "## %3d:%02d:%02d " % (secs // (60*60), (secs // 60) % 60, secs % 60) def replace_in_stmt(self, stmt, pat, repl): if stmt == pat: @@ -294,11 +294,12 @@ class SmtIo: def p_read(self): assert self.p is not None - assert self.p_running if self.p_next is not None: data = self.p_next self.p_next = None return data + if not self.p_running: + return "" return self.p_queue.get() def p_poll(self): @@ -580,12 +581,12 @@ class SmtIo: if count_brackets == 0: break if self.solver != "dummy" and self.p.poll(): - print("SMT Solver terminated unexpectedly: %s" % "".join(stmt), flush=True) + print("%s Solver terminated unexpectedly: %s" % (self.timestamp(), "".join(stmt)), flush=True) sys.exit(1) stmt = "".join(stmt) if stmt.startswith("(error"): - print("SMT Solver Error: %s" % stmt, file=sys.stderr, flush=True) + print("%s Solver Error: %s" % (self.timestamp(), stmt), flush=True) if self.solver != "dummy": self.p_close() sys.exit(1) @@ -652,7 +653,15 @@ class SmtIo: print("(check-sat)", file=self.debug_file) self.debug_file.flush() - assert result in ["sat", "unsat"] + if result not in ["sat", "unsat"]: + if result == "": + print("%s Unexpected EOF response from solver." % (self.timestamp()), flush=True) + else: + print("%s Unexpected response from solver: %s" % (self.timestamp(), result), flush=True) + if self.solver != "dummy": + self.p_close() + sys.exit(1) + return result def parse(self, stmt): From 64ea55056a4fca35fa4e956d40da98c20bb8d730 Mon Sep 17 00:00:00 2001 From: Edmond Cote Date: Tue, 20 Mar 2018 15:50:50 -0700 Subject: [PATCH 010/184] Rename rename to renames Create TCL alias for rename command. Using renames. Following the same convention as proc -> procs. --- kernel/yosys.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index cade09048..49d644548 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -598,6 +598,8 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a std::string tcl_command_name = it.first; if (tcl_command_name == "proc") tcl_command_name = "procs"; + else if (tcl_command_name == "rename") + tcl_command_name = "renames"; Tcl_CmdInfo info; if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) { log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str()); @@ -637,9 +639,9 @@ struct TclPass : public Pass { log("Use 'yosys cmd' to run the yosys command 'cmd' from tcl.\n"); log("\n"); log("The tcl command 'yosys -import' can be used to import all yosys\n"); - log("commands directly as tcl commands to the tcl shell. The yosys\n"); - log("command 'proc' is wrapped using the tcl command 'procs' in order\n"); - log("to avoid a name collision with the tcl builtin command 'proc'.\n"); + log("commands directly as tcl commands to the tcl shell. Yosys commands\n"); + log("'proc' and 'rename' are wrapped to tcl commands 'procs' and 'renames'\n"); + log("in order to avoid a name collision with the built in commands.\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { From 315d5e32bfb63a2b4be2dc5e729125c420b164a4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 26 Mar 2018 13:04:10 +0200 Subject: [PATCH 011/184] Fix handling of unclocked immediate assertions in Verific front-end Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 7 ++++- frontends/verific/verific.h | 2 +- frontends/verific/verificsva.cc | 50 +++++++++++++++++++++++---------- 3 files changed, 42 insertions(+), 17 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9f61d69a4..793e296f4 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1297,7 +1297,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se // ================================================================== -VerificClocking::VerificClocking(VerificImporter *importer, Net *net) +VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only) { module = importer->module; @@ -1320,6 +1320,11 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net) body_net = body_inst->GetInput2(); } } + else + { + if (sva_at_only) + return; + } if (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE) { diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 877d79057..9e3e39695 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -42,7 +42,7 @@ struct VerificClocking { bool posedge = true; VerificClocking() { } - VerificClocking(VerificImporter *importer, Verific::Net *net); + VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false); RTLIL::Cell *addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value = Const()); RTLIL::Cell *addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value); RTLIL::Cell *addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q); diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index c9c341516..1a1000b19 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1543,20 +1543,33 @@ struct VerificSvaImporter RTLIL::IdString root_name = module->uniquify(importer->mode_names || root->IsUserDeclared() ? RTLIL::escape_id(root->Name()) : NEW_ID); - clocking = VerificClocking(importer, root->GetInput()); - - if (clocking.body_net == nullptr) - parser_error(stringf("Failed to parse SVA clocking"), root); - // parse SVA sequence into trigger signal - Net *net = clocking.body_net; - SigBit accept_bit = State::S0, reject_bit = State::S0; + clocking = VerificClocking(importer, root->GetInput(), true); + SigBit accept_bit = State::S0, reject_bit = State::S0; - if (mode_assert || mode_assume) { - parse_property(net, nullptr, &reject_bit); - } else { - parse_property(net, &accept_bit, nullptr); + if (clocking.body_net == nullptr) + { + if (clocking.clock_net != nullptr || clocking.enable_net != nullptr || clocking.disable_net != nullptr || clocking.cond_net != nullptr) + parser_error(stringf("Failed to parse SVA clocking"), root); + + if (mode_assert || mode_assume) { + log_ping(); + reject_bit = module->Not(NEW_ID, parse_expression(root->GetInput())); + } else { + log_ping(); + accept_bit = parse_expression(root->GetInput()); + } + } + else + { + if (mode_assert || mode_assume) { + log_ping(); + parse_property(clocking.body_net, nullptr, &reject_bit); + } else { + log_ping(); + parse_property(clocking.body_net, &accept_bit, nullptr); + } } if (mode_trigger) @@ -1570,10 +1583,17 @@ struct VerificSvaImporter // add final FF stage - SigBit sig_a_q = module->addWire(NEW_ID); - SigBit sig_en_q = module->addWire(NEW_ID); - clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0); - clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0); + SigBit sig_a_q, sig_en_q; + + if (clocking.body_net == nullptr) { + sig_a_q = sig_a; + sig_en_q = sig_en; + } else { + sig_a_q = module->addWire(NEW_ID); + sig_en_q = module->addWire(NEW_ID); + clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0); + clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0); + } // generate assert/assume/cover cell From 491c352da7b656aa3979754e0a03182dfaabdd13 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 26 Mar 2018 21:19:00 +0200 Subject: [PATCH 012/184] Add .sv support to "hierarchy -libdir" --- passes/hierarchy/hierarchy.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 898763c64..71b0cf622 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -179,6 +179,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check goto loaded_module; } + filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".sv"; + if (check_file_exists(filename)) { + Frontend::frontend_call(design, NULL, filename, "verilog -sv"); + goto loaded_module; + } + filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; if (check_file_exists(filename)) { Frontend::frontend_call(design, NULL, filename, "ilang"); From 6f681c4f8296d5776d7773c2f7eb62398bf11507 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Mar 2018 00:39:01 +0200 Subject: [PATCH 013/184] Fix build for new ABC location on github, also update ABC to a2d59be --- Makefile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index af29ff414..0b8af9f8f 100644 --- a/Makefile +++ b/Makefile @@ -102,9 +102,9 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = 6e3c24b3308a +ABCREV = a2d59be ABCPULL = 1 -ABCURL ?= https://bitbucket.org/alanmi/abc +ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 # set ABCEXTERNAL = to use an external ABC instance @@ -442,14 +442,14 @@ yosys-config: misc/yosys-config.in abc/abc-$(ABCREV)$(EXE): $(P) ifneq ($(ABCREV),default) - $(Q) if ( cd abc 2> /dev/null && hg identify; ) | grep -q +; then \ + $(Q) if ( cd abc 2> /dev/null && ! git diff-index --quiet HEAD; ); then \ echo 'REEBE: NOP pbagnvaf ybpny zbqvsvpngvbaf! Frg NOPERI=qrsnhyg va Lbflf Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \ fi - $(Q) if test "`cd abc 2> /dev/null && hg identify | cut -f1 -d' '`" != "$(ABCREV)"; then \ + $(Q) if test "`cd abc 2> /dev/null && git rev-parse --short HEAD`" != "$(ABCREV)"; then \ test $(ABCPULL) -ne 0 || { echo 'REEBE: NOP abg hc gb qngr naq NOPCHYY frg gb 0 va Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; exit 1; }; \ echo "Pulling ABC from $(ABCURL):"; set -x; \ - test -d abc || hg clone --insecure $(ABCURL) abc; \ - cd abc && $(MAKE) DEP= clean && hg pull --insecure && hg update -r $(ABCREV); \ + test -d abc || git clone $(ABCURL) abc; \ + cd abc && $(MAKE) DEP= clean && git fetch origin master && git checkout $(ABCREV); \ fi endif $(Q) rm -f abc/abc-[0-9a-f]* From 77bd645c35225d4fa1a1c632457acfb47b7388eb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Mar 2018 02:11:20 +0200 Subject: [PATCH 014/184] Add $mem support to SMT2 clock tagging Signed-off-by: Clifford Wolf --- backends/smt2/smt2.cc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 47c993d05..2fb6d4da9 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -135,6 +135,24 @@ struct Smt2Worker log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n", log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type)); + if (cell->type.in("$mem") && conn.first.in("\\RD_CLK", "\\WR_CLK")) + { + SigSpec clk = sigmap(conn.second); + for (int i = 0; i < GetSize(clk); i++) + { + if (clk[i].wire == nullptr) + continue; + + if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_ENABLE" : "\\WR_CLK_ENABLE")[i] != State::S1) + continue; + + if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_POLARITY" : "\\WR_CLK_POLARITY")[i] == State::S1) + clock_posedge.insert(clk[i]); + else + clock_negedge.insert(clk[i]); + } + } + else if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_") && conn.first.in("\\CLK", "\\C")) { bool posedge = (cell->type == "$_DFF_N_") || (cell->type == "$dff" && cell->getParam("\\CLK_POLARITY").as_bool()); From f93f8aaa114b06e046a107c9e1f77046a4b5b1fc Mon Sep 17 00:00:00 2001 From: Sergi Granell Date: Tue, 27 Mar 2018 09:35:20 +0200 Subject: [PATCH 015/184] passes/hierarchy: Reduce code duplication in expand_module This also makes it easier to add new file extensions support. Signed-off-by: Sergi Granell --- passes/hierarchy/hierarchy.cc | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 71b0cf622..21a232572 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -173,22 +173,20 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &dir : libdirs) { - filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v"; - if (check_file_exists(filename)) { - Frontend::frontend_call(design, NULL, filename, "verilog"); - goto loaded_module; - } + static const std::map extensions_map = + { + {".v", "verilog"}, + {".sv", "verilog -sv"}, + {".il", "ilang"} + }; - filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".sv"; - if (check_file_exists(filename)) { - Frontend::frontend_call(design, NULL, filename, "verilog -sv"); - goto loaded_module; - } - - filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; - if (check_file_exists(filename)) { - Frontend::frontend_call(design, NULL, filename, "ilang"); - goto loaded_module; + for (auto &ext : extensions_map) + { + filename = dir + "/" + RTLIL::unescape_id(cell->type) + ext.first; + if (check_file_exists(filename)) { + Frontend::frontend_call(design, NULL, filename, ext.second); + goto loaded_module; + } } } From ee3c12d6d9cbdb213c3c203d563c040867c70770 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Mar 2018 14:12:57 +0200 Subject: [PATCH 016/184] Chenged "extensions_map" to "extensions_list" in hierarchy.cc Signed-off-by: Clifford Wolf --- passes/hierarchy/hierarchy.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 21a232572..ba960faf4 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -173,14 +173,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &dir : libdirs) { - static const std::map extensions_map = + static const vector> extensions_list = { {".v", "verilog"}, {".sv", "verilog -sv"}, {".il", "ilang"} }; - for (auto &ext : extensions_map) + for (auto &ext : extensions_list) { filename = dir + "/" + RTLIL::unescape_id(cell->type) + ext.first; if (check_file_exists(filename)) { From 6378e2cd46711fed551ecf3201cee1f174d7053d Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Sun, 4 Mar 2018 23:35:08 +0200 Subject: [PATCH 017/184] First draft of Verilog parser support for specify blocks and parameters. The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST --- frontends/verilog/verilog_lexer.l | 3 + frontends/verilog/verilog_parser.y | 169 ++++++++++++++++++++++++++++- tests/simple/specify.v | 31 ++++++ 3 files changed, 201 insertions(+), 2 deletions(-) create mode 100644 tests/simple/specify.v diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index d6d00c371..32d7738cf 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -145,6 +145,9 @@ YOSYS_NAMESPACE_END "endfunction" { return TOK_ENDFUNCTION; } "task" { return TOK_TASK; } "endtask" { return TOK_ENDTASK; } +"specify" { return TOK_SPECIFY; } +"endspecify" { return TOK_ENDSPECIFY; } +"specparam" { return TOK_SPECPARAM; } "package" { SV_KEYWORD(TOK_PACKAGE); } "endpackage" { SV_KEYWORD(TOK_ENDPACKAGE); } "parameter" { return TOK_PARAMETER; } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index ba2fc036e..3dd54f532 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -110,7 +110,7 @@ static void free_attr(std::map *al) %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT -%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK +%token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK TOK_SPECIFY TOK_ENDSPECIFY TOK_SPECPARAM %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED @@ -476,7 +476,7 @@ module_body: /* empty */; module_body_stmt: - task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt | + task_func_decl | specify_block |param_decl | localparam_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl; checker_decl: @@ -634,6 +634,171 @@ task_func_body: task_func_body behavioral_stmt | /* empty */; +specify_block: + TOK_SPECIFY specify_item_opt TOK_ENDSPECIFY | + TOK_SPECIFY TOK_ENDSPECIFY ; + +specify_item_opt: + specify_item_opt specify_item | + specify_item ; + +specify_item: + specparam_declaration + // | pulsestyle_declaration + // | showcancelled_declaration + | path_declaration + // | system_timing_declaration + ; + +specparam_declaration: + TOK_SPECPARAM list_of_specparam_assignments ';' | + TOK_SPECPARAM specparam_range list_of_specparam_assignments ';' ; + +// IEEE 1364-2005 calls this sinmply 'range' but the current 'range' rule allows empty match +// and the 'non_opt_range' rule allows index ranges not allowed by 1364-2005 +// exxxxtending this for SV specparam would change this anyhow +specparam_range: + '[' constant_expression ':' constant_expression ']' ; + +list_of_specparam_assignments: + specparam_assignment | list_of_specparam_assignments ',' specparam_assignment; + +specparam_assignment: + TOK_ID '=' constant_mintypmax_expression ; + +/* +pulsestyle_declaration : + ; + +showcancelled_declaration : + ; +*/ + +path_declaration : + simple_path_declaration + // | edge_sensitive_path_declaration + // | state_dependent_path_declaration + ; + +simple_path_declaration : + parallel_path_description '=' path_delay_value ';' + // | full_path_description '=' path_delay_value ';' + ; + +path_delay_value : + //list_of_path_delay_expressions + '(' list_of_path_delay_expressions ')' + ; + +list_of_path_delay_expressions : +/* + t_path_delay_expression + | trise_path_delay_expression ',' tfall_path_delay_expression + | trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression + | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ',' + tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression + | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ',' + tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ',' + t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ',' + tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression +*/ + path_delay_expression + | path_delay_expression ',' path_delay_expression + | path_delay_expression ',' path_delay_expression ',' path_delay_expression + | path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + path_delay_expression ',' path_delay_expression ',' path_delay_expression + | path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + path_delay_expression ',' path_delay_expression ',' path_delay_expression + ; + +parallel_path_description : + '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; + +opt_polarity_operator : + '+' + | '-' + | ; + +// Good enough for the time being +specify_input_terminal_descriptor : + TOK_ID ; + +// Good enough for the time being +specify_output_terminal_descriptor : + TOK_ID ; + +/* +system_timing_declaration : + ; +*/ + +/* +t_path_delay_expression : + path_delay_expression; + +trise_path_delay_expression : + path_delay_expression; + +tfall_path_delay_expression : + path_delay_expression; + +tz_path_delay_expression : + path_delay_expression; + +t01_path_delay_expression : + path_delay_expression; + +t10_path_delay_expression : + path_delay_expression; + +t0z_path_delay_expression : + path_delay_expression; + +tz1_path_delay_expression : + path_delay_expression; + +t1z_path_delay_expression : + path_delay_expression; + +tz0_path_delay_expression : + path_delay_expression; + +t0x_path_delay_expression : + path_delay_expression; + +tx1_path_delay_expression : + path_delay_expression; + +t1x_path_delay_expression : + path_delay_expression; + +tx0_path_delay_expression : + path_delay_expression; + +txz_path_delay_expression : + path_delay_expression; + +tzx_path_delay_expression : + path_delay_expression; +*/ + +path_delay_expression : + constant_mintypmax_expression; + +constant_mintypmax_expression : + constant_expression + | constant_expression ':' constant_expression ':' constant_expression + ; + +// for the time being this is OK, but we may write our own expr here. +// as I'm not sure it is legal to use a full expr here (probably not) +// On the other hand, other rules requiring constant expressions also use 'expr' +// (such as param assignment), so we may leave this as-is, perhaps assing runtime checks for constant-ness +constant_expression: + expr ; + param_signed: TOK_SIGNED { astbuf1->is_signed = true; diff --git a/tests/simple/specify.v b/tests/simple/specify.v new file mode 100644 index 000000000..74563509e --- /dev/null +++ b/tests/simple/specify.v @@ -0,0 +1,31 @@ +module test_specify; + +specparam a=1; + +specify +endspecify + +specify +(A => B) = ( 1 ) ; +(A- => B) = ( 1,2 ) ; +(A+ => B) = ( 1,2,3 ) ; +(A => B) = ( + 1.1, 2, 3, + 4, 5.5, 6.6 +) ; +(A => B) = ( + 1.1, 2, 3, + 4, 5.5, 6.6 , + 7.7, 8.8, 9, + 10.1, 11, 12 +) ; +specparam a=1; +specparam [1:2] asasa=1; +endspecify + +specify +specparam a=1:2:3; +endspecify + +endmodule + From 5e49ee5c2d52d504334a6cbbf7d9e0250e00a515 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Mar 2018 14:31:19 +0200 Subject: [PATCH 018/184] Fix tests/simple/specify.v Signed-off-by: Clifford Wolf --- tests/simple/specify.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/simple/specify.v b/tests/simple/specify.v index 74563509e..f19418d90 100644 --- a/tests/simple/specify.v +++ b/tests/simple/specify.v @@ -19,12 +19,12 @@ specify 7.7, 8.8, 9, 10.1, 11, 12 ) ; -specparam a=1; +specparam b=1; specparam [1:2] asasa=1; endspecify specify -specparam a=1:2:3; +specparam c=1:2:3; endspecify endmodule From 0acea3548b54a2acf6f3b554e6878f884a4414fe Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Mar 2018 15:04:10 +0200 Subject: [PATCH 019/184] Set stack size to at least 128 MB (large stack needed for parsing huge expressions) Signed-off-by: Clifford Wolf --- kernel/driver.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/kernel/driver.cc b/kernel/driver.cc index 97a78cd16..3c16e5fd4 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -35,6 +35,7 @@ #include #ifdef __linux__ +# include # include # include #endif @@ -416,6 +417,18 @@ int main(int argc, char **argv) if (print_stats) log_hasher = new SHA1; +#if defined(__linux__) + // set stack size to >= 128 MB + { + struct rlimit rl; + const rlim_t stack_size = 128L * 1024L * 1024L; + if (getrlimit(RLIMIT_STACK, &rl) == 0 && rl.rlim_cur < stack_size) { + rl.rlim_cur = stack_size; + setrlimit(RLIMIT_STACK, &rl); + } + } +#endif + yosys_setup(); log_error_atexit = yosys_atexit; From 665eec3d531e0da3a2d599fd9869d81dfa8c3966 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 29 Mar 2018 12:38:41 +0200 Subject: [PATCH 020/184] Removed $timescale from "sat" command VCD writer Signed-off-by: Clifford Wolf --- passes/sat/sat.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index a6ac7afd4..6c0834deb 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -691,7 +691,6 @@ struct SatHelper // VCD has some limits on internal (non-display) identifier names, so make legal ones std::map vcdnames; - fprintf(f, "$timescale 1ns\n"); // arbitrary time scale since actual clock period is unknown/unimportant fprintf(f, "$scope module %s $end\n", module->name.c_str()); for (auto &info : modelInfo) { From a48c7e5abfc1dd406039991ebac73db59c8a432f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 29 Mar 2018 12:45:31 +0200 Subject: [PATCH 021/184] Bugfix in smtio.py VCD file generator Signed-off-by: Clifford Wolf --- backends/smt2/smtio.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index 215b4a008..d8e095e6b 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -991,7 +991,7 @@ class MkVcd: for i in range(len(uipath)): uipath[i] = re.sub(r"\[([^\]]*)\]", r"<\1>", uipath[i]) - while uipath[:len(scope)] != scope[:-1]: + while uipath[:len(scope)] != scope: print("$upscope $end", file=self.f) scope = scope[:-1] From dd5fab69c135135fa46b6325a39c184a2ddc6156 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 29 Mar 2018 21:59:30 +0200 Subject: [PATCH 022/184] Add smtio status msgs when --progress is inactive Signed-off-by: Clifford Wolf --- backends/smt2/smtio.py | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index d8e095e6b..bf72e8916 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -302,13 +302,13 @@ class SmtIo: return "" return self.p_queue.get() - def p_poll(self): + def p_poll(self, timeout=0.1): assert self.p is not None assert self.p_running if self.p_next is not None: return False try: - self.p_next = self.p_queue.get(True, 0.1) + self.p_next = self.p_queue.get(True, timeout) return False except Empty: return True @@ -646,6 +646,27 @@ class SmtIo: print("\b \b" * num_bs, end="", file=sys.stderr) sys.stderr.flush() + else: + count = 0 + while self.p_poll(60): + count += 1 + msg = None + + if count == 1: + msg = "1 minute" + + elif count in [5, 10, 15, 30]: + msg = "%d minutes" % count + + elif count == 60: + msg = "1 hour" + + elif count % 60 == 0: + msg = "%d hours" % (count // 60) + + if msg is not None: + print("%s waiting for solver (%s)" % (self.timestamp(), msg), flush=True) + result = self.read() if self.debug_file: From 8fe9cdf36428b07ab22e9f831470e7e4c37978e2 Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Sat, 31 Mar 2018 02:54:26 -0700 Subject: [PATCH 023/184] coolrunner2: Add extraction for TFFs --- techlibs/coolrunner2/Makefile.inc | 1 + techlibs/coolrunner2/synth_coolrunner2.cc | 12 +++++++ techlibs/coolrunner2/tff_extract.v | 41 +++++++++++++++++++++++ 3 files changed, 54 insertions(+) create mode 100644 techlibs/coolrunner2/tff_extract.v diff --git a/techlibs/coolrunner2/Makefile.inc b/techlibs/coolrunner2/Makefile.inc index 96bbb0f47..d62c9960c 100644 --- a/techlibs/coolrunner2/Makefile.inc +++ b/techlibs/coolrunner2/Makefile.inc @@ -4,4 +4,5 @@ OBJS += techlibs/coolrunner2/coolrunner2_sop.o $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v)) $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v)) +$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/tff_extract.v)) $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib)) diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index 183282629..5d9e3cc90 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -149,6 +149,16 @@ struct SynthCoolrunner2Pass : public ScriptPass run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib"); } + if (check_label("map_tff")) + { + // This is quite hacky. By telling abc that it can only use AND and XOR gates, abc will try and use XOR + // gates "whenever possible." This will hopefully cause toggle flip-flop structures to turn into an XOR + // connected to a D flip-flop. We then match on these and convert them into XC2 TFF cells. + run("abc -g AND,XOR"); + run("clean"); + run("extract -map +/coolrunner2/tff_extract.v"); + } + if (check_label("map_pla")) { run("abc -sop -I 40 -P 56"); @@ -160,6 +170,8 @@ struct SynthCoolrunner2Pass : public ScriptPass run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib"); run("dffinit -ff FDCP Q INIT"); run("dffinit -ff FDCP_N Q INIT"); + run("dffinit -ff FTCP Q INIT"); + run("dffinit -ff FTCP_N Q INIT"); run("dffinit -ff LDCP Q INIT"); run("dffinit -ff LDCP_N Q INIT"); run("coolrunner2_sop"); diff --git a/techlibs/coolrunner2/tff_extract.v b/techlibs/coolrunner2/tff_extract.v new file mode 100644 index 000000000..b4237dd18 --- /dev/null +++ b/techlibs/coolrunner2/tff_extract.v @@ -0,0 +1,41 @@ +module FTCP (C, PRE, CLR, T, Q); + input C, PRE, CLR, T; + output wire Q; + + wire xorout; + + $_XOR_ xorgate ( + .A(T), + .B(Q), + .Y(xorout), + ); + + $_DFFSR_PPP_ dff ( + .C(C), + .D(xorout), + .Q(Q), + .S(PRE), + .R(CLR), + ); +endmodule + +module FTCP_N (C, PRE, CLR, T, Q); + input C, PRE, CLR, T; + output wire Q; + + wire xorout; + + $_XOR_ xorgate ( + .A(T), + .B(Q), + .Y(xorout), + ); + + $_DFFSR_NPP_ dff ( + .C(C), + .D(xorout), + .Q(Q), + .S(PRE), + .R(CLR), + ); +endmodule From cfa3753b89c684b66e2cb164226a3358493e5232 Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Sat, 31 Mar 2018 02:56:11 -0700 Subject: [PATCH 024/184] coolrunner2: Split multi-bit nets The PAR tool doesn't expect any "dangling" nets with no drivers nor sinks. By splitting the nets, clean removes them. --- techlibs/coolrunner2/synth_coolrunner2.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index 5d9e3cc90..2e94c3449 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -178,6 +178,7 @@ struct SynthCoolrunner2Pass : public ScriptPass run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO"); run("attrmvcp -attr src -attr LOC t:IOBUFE n:*"); run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*"); + run("splitnets"); run("clean"); } From 14e49fb05737cfb02217b2aaf14d9f5d9e1859da Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Sat, 31 Mar 2018 03:54:48 -0700 Subject: [PATCH 025/184] coolrunner2: Add an ANDTERM/XOR between chained FFs In some cases (e.g. the low bits of counters) the design might end up with a flip-flop whose input is directly driven by another flip-flop. This isn't possible in the Coolrunner-II architecture, so add a single AND term and XOR in this case. --- techlibs/coolrunner2/coolrunner2_sop.cc | 58 +++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc index b57214ccb..431e0a127 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cc +++ b/techlibs/coolrunner2/coolrunner2_sop.cc @@ -250,6 +250,64 @@ struct Coolrunner2SopPass : public Pass { } } + // In some cases we can get a FF feeding straight into an FF. This is not possible, so we need to insert + // some AND/XOR cells in the middle to make it actually work. + + // Find all the FF outputs + pool sig_fed_by_ff; + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" || + cell->type == "\\LDCP" || cell->type == "\\LDCP_N" || + cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" || + cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE") + { + auto output = sigmap(cell->getPort("\\Q")[0]); + sig_fed_by_ff.insert(output); + } + } + + // Look at all the FF inputs + for (auto cell : module->selected_cells()) + { + if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" || + cell->type == "\\LDCP" || cell->type == "\\LDCP_N" || + cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" || + cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE") + { + SigBit input; + if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP") + input = sigmap(cell->getPort("\\T")[0]); + else + input = sigmap(cell->getPort("\\D")[0]); + + if (sig_fed_by_ff[input]) + { + printf("Buffering input to \"%s\"\n", cell->name.c_str()); + + auto and_to_xor_wire = module->addWire(NEW_ID); + auto xor_to_ff_wire = module->addWire(NEW_ID); + + auto and_cell = module->addCell(NEW_ID, "\\ANDTERM"); + and_cell->setParam("\\TRUE_INP", 1); + and_cell->setParam("\\COMP_INP", 0); + and_cell->setPort("\\OUT", and_to_xor_wire); + and_cell->setPort("\\IN", input); + and_cell->setPort("\\IN_B", SigSpec()); + + auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR"); + xor_cell->setParam("\\INVERT_OUT", false); + xor_cell->setPort("\\IN_PTC", and_to_xor_wire); + xor_cell->setPort("\\OUT", xor_to_ff_wire); + + if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP") + cell->setPort("\\T", xor_to_ff_wire); + else + cell->setPort("\\D", xor_to_ff_wire); + } + } + } + // Actually do the removal now that we aren't iterating for (auto cell : cells_to_remove) { From 93985d91b1d3e4dacf6de5563fc56f82d9123d38 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 31 Mar 2018 14:23:57 +0200 Subject: [PATCH 026/184] Remove left-over log_ping debug commands.. oops. Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 1a1000b19..8dc213a18 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1554,20 +1554,16 @@ struct VerificSvaImporter parser_error(stringf("Failed to parse SVA clocking"), root); if (mode_assert || mode_assume) { - log_ping(); reject_bit = module->Not(NEW_ID, parse_expression(root->GetInput())); } else { - log_ping(); accept_bit = parse_expression(root->GetInput()); } } else { if (mode_assert || mode_assume) { - log_ping(); parse_property(clocking.body_net, nullptr, &reject_bit); } else { - log_ping(); parse_property(clocking.body_net, &accept_bit, nullptr); } } From efed2420d686c35f79c4f68e56b460f8e534a6ea Mon Sep 17 00:00:00 2001 From: c60k28 Date: Sat, 31 Mar 2018 22:48:47 -0600 Subject: [PATCH 027/184] Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device --- techlibs/achronix/Makefile.inc | 2 +- techlibs/achronix/speedster22i/cells_map.v | 66 ++++++--------- techlibs/achronix/speedster22i/cells_sim.v | 83 ++++--------------- .../{synth_speedster.cc => synth_achronix.cc} | 20 ++--- techlibs/intel/cyclone10/cells_map.v | 20 +++-- techlibs/intel/cycloneiv/cells_map.v | 20 +++-- techlibs/intel/cycloneive/arith_map.v | 51 +++++++++++- techlibs/intel/cycloneive/cells_map.v | 21 +++-- techlibs/intel/cyclonev/cells_map.v | 75 ++++++++++------- techlibs/intel/max10/cells_map.v | 24 ++++-- techlibs/intel/synth_intel.cc | 27 +++++- 11 files changed, 232 insertions(+), 177 deletions(-) rename techlibs/achronix/{synth_speedster.cc => synth_achronix.cc} (92%) diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc index affe0334a..994cf0015 100755 --- a/techlibs/achronix/Makefile.inc +++ b/techlibs/achronix/Makefile.inc @@ -1,5 +1,5 @@ -OBJS += techlibs/achronix/synth_speedster.o +OBJS += techlibs/achronix/synth_achronix.o $(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v)) $(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v)) diff --git a/techlibs/achronix/speedster22i/cells_map.v b/techlibs/achronix/speedster22i/cells_map.v index 90f87826d..95f5d59c5 100755 --- a/techlibs/achronix/speedster22i/cells_map.v +++ b/techlibs/achronix/speedster22i/cells_map.v @@ -16,53 +16,25 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ -// Normal mode DFF negedge clk, negedge reset -module \$_DFF_N_ (input D, C, output Q); - parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule -// Normal mode DFF -module \$_DFF_P_ (input D, C, output Q); - parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule - -// Async Active Low Reset DFF -module \$_DFF_PN0_ (input D, C, R, output Q); - parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule -// Async Active High Reset DFF -module \$_DFF_PP0_ (input D, C, R, output Q); - parameter WYSIWYG="TRUE"; - wire R_i = ~ R; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule -// Async Active Low Reset DFF -module \$_DFF_PN0_ (input D, C, R, output Q); - parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); -endmodule -/* */ -module \$__DFFE_PP0 (input D, C, E, R, output Q); - parameter WYSIWYG="TRUE"; - wire E_i = ~ E; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); -endmodule +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Achronix eFPGA technology mapping. User must first simulate the generated \ +// > netlist before going to test it on board/custom chip. +// > Input/Output buffers < // Input buffer map module \$__inpad (input I, output O); PADIN _TECHMAP_REPLACE_ (.padout(O), .padin(I)); endmodule - // Output buffer map module \$__outpad (input I, output O); PADOUT _TECHMAP_REPLACE_ (.padout(O), .padin(I), .oe(1'b1)); endmodule +// > end buffers < +// > Look-Up table < +// > VT: I still think Achronix folks would have choosen a better \ +// > logic architecture. // LUT Map -/* 0 -> datac - 1 -> cin */ module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; @@ -70,19 +42,31 @@ module \$lut (A, Y); output Y; generate if (WIDTH == 1) begin - assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function + // VT: This is not consistent and ACE will complain: assign Y = ~A[0]; + LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ + (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0)); end else if (WIDTH == 2) begin - LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0),.din3(1'b0)); + LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ + (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0)); end else if(WIDTH == 3) begin - LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]),.din3(1'b0)); + LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ + (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0)); end else if(WIDTH == 4) begin - LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3])); + LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ + (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3])); end else wire _TECHMAP_FAIL_ = 1; endgenerate -endmodule // +endmodule +// > end LUT < +// > Flops < +// DFF flop +module \$_DFF_P_ (input D, C, output Q); + DFF _TECHMAP_REPLACE_ + (.q(Q), .d(D), .ck(C)); +endmodule diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v index 24c57c41a..da23fed7e 100755 --- a/techlibs/achronix/speedster22i/cells_sim.v +++ b/techlibs/achronix/speedster22i/cells_sim.v @@ -16,50 +16,31 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Achronix eFPGA technology sim models. User must first simulate the generated \ +// > netlist before going to test it on board/custom chip. +// > Changelog: 1) Removed unused VCC/GND modules +// > 2) Altera comments here (?). Removed. +// > 3) Reusing LUT sim model, removed wrong wires and parameters. -module VCC (output V); - assign V = 1'b1; -endmodule // VCC - -module GND (output G); - assign G = 1'b0; -endmodule // GND - -/* Altera MAX10 devices Input Buffer Primitive */ module PADIN (output padout, input padin); assign padout = padin; -endmodule // fiftyfivenm_io_ibuf +endmodule -/* Altera MAX10 devices Output Buffer Primitive */ module PADOUT (output padout, input padin, input oe); assign padout = padin; assign oe = oe; -endmodule // fiftyfivenm_io_obuf +endmodule -/* Altera MAX10 4-input non-fracturable LUT Primitive */ module LUT4 (output dout, input din0, din1, din2, din3); -/* Internal parameters which define the behaviour - of the LUT primitive. - lut_mask define the lut function, can be expressed in 16-digit bin or hex. - sum_lutc_input define the type of LUT (combinational | arithmetic). - dont_touch for retiming || carry options. - lpm_type for WYSIWYG */ - -parameter lut_function = 16'hFFFF; -//parameter dont_touch = "off"; -//parameter lpm_type = "fiftyfivenm_lcell_comb"; -//parameter sum_lutc_input = "datac"; - -reg [1:0] lut_type; -reg cout_rt; +parameter [15:0] lut_function = 16'hFFFF; reg combout_rt; wire dataa_w; wire datab_w; wire datac_w; wire datad_w; -wire cin_w; assign dataa_w = din0; assign datab_w = din1; @@ -78,49 +59,21 @@ reg [1:0] s1; s1 = datab ? s2[3:2] : s2[1:0]; lut_data = dataa ? s1[1] : s1[0]; end - endfunction -initial begin - /*if (sum_lutc_input == "datac")*/ lut_type = 0; - /*else - if (sum_lutc_input == "cin") lut_type = 1; - else begin - $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input); - $finish(); - end*/ -end - always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin - if (lut_type == 0) begin // logic function - combout_rt = lut_data(lut_function, dataa_w, datab_w, - datac_w, datad_w); - end - else if (lut_type == 1) begin // arithmetic function - combout_rt = lut_data(lut_function, dataa_w, datab_w, - cin_w, datad_w); - end - cout_rt = lut_data(lut_function, dataa_w, datab_w, cin_w, 'b0); + combout_rt = lut_data(lut_function, dataa_w, datab_w, + datac_w, datad_w); end - assign dout = combout_rt & 1'b1; -//assign cout = cout_rt & 1'b1; - -endmodule // fiftyfivenm_lcell_comb - -/* Altera MAX10 D Flip-Flop Primitive */ -// TODO: Implement advanced simulation functions -module dffeas ( output q, - input d, clk, clrn, prn, ena, - input asdata, aload, sclr, sload ); - -parameter power_up="dontcare"; -parameter is_wysiwyg="false"; - reg q; - - always @(posedge clk) - q <= d; +endmodule +module DFF (output q, + input d, ck); + reg q; + always @(posedge ck) + q <= d; + endmodule diff --git a/techlibs/achronix/synth_speedster.cc b/techlibs/achronix/synth_achronix.cc similarity index 92% rename from techlibs/achronix/synth_speedster.cc rename to techlibs/achronix/synth_achronix.cc index 3808af6f1..7f4503070 100755 --- a/techlibs/achronix/synth_speedster.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -25,14 +25,14 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct SynthIntelPass : public ScriptPass { - SynthIntelPass() : ScriptPass("synth_speedster", "synthesis for Acrhonix Speedster22i FPGAs.") { } +struct SynthAchronixPass : public ScriptPass { + SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { } virtual void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" synth_speedster [options]\n"); + log(" synth_achronix [options]\n"); log("\n"); log("This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.\n"); log("\n"); @@ -110,7 +110,7 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This comannd only operates on fully selected designs!\n"); - log_header(design, "Executing SYNTH_SPEEDSTER pass.\n"); + log_header(design, "Executing SYNTH_ACHRONIX pass.\n"); log_push(); run_script(design, run_from, run_to); @@ -146,9 +146,9 @@ struct SynthIntelPass : public ScriptPass { run("opt -undriven -fine"); run("dffsr2dff"); run("dff2dffe -direct-match $_DFF_*"); - run("opt -full"); + run("opt -fine"); run("techmap -map +/techmap.v"); - run("opt -fast"); + run("opt -full"); run("clean -purge"); run("setundef -undriven -zero"); if (retime || help_mode) @@ -157,7 +157,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_luts")) { - run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + run("abc -lut 4" + string(retime ? " -dff" : "")); run("clean"); } @@ -165,7 +165,7 @@ struct SynthIntelPass : public ScriptPass { { run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I"); run("techmap -map +/achronix/speedster22i/cells_map.v"); - run("dffinit -ff dffeas Q INIT"); + // VT: not done yet run("dffinit -highlow -ff DFF q power_up"); run("clean -purge"); } @@ -179,10 +179,10 @@ struct SynthIntelPass : public ScriptPass { if (check_label("vout")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -nodec -attr2comment -defparam -nohex -renameprefix yosys_ %s", + run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix syn_ %s", help_mode ? "" : vout_file.c_str())); } } -} SynthIntelPass; +} SynthAchronixPass; PRIVATE_NAMESPACE_END diff --git a/techlibs/intel/cyclone10/cells_map.v b/techlibs/intel/cyclone10/cells_map.v index 8ac5a55ec..c2f6f403c 100644 --- a/techlibs/intel/cyclone10/cells_map.v +++ b/techlibs/intel/cyclone10/cells_map.v @@ -16,33 +16,43 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Intel FPGA technology mapping. User must first simulate the generated \ +// > netlist before going to test it on board. +// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed. + // Normal mode DFF negedge clk, negedge reset module \$_DFF_N_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Normal mode DFF module \$_DFF_P_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active Low Reset DFF module \$_DFF_PN0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active High Reset DFF module \$_DFF_PP0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire R_i = ~ R; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire E_i = ~ E; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); endmodule // Input buffer map diff --git a/techlibs/intel/cycloneiv/cells_map.v b/techlibs/intel/cycloneiv/cells_map.v index b991fbae7..191488430 100644 --- a/techlibs/intel/cycloneiv/cells_map.v +++ b/techlibs/intel/cycloneiv/cells_map.v @@ -16,33 +16,43 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Intel FPGA technology mapping. User must first simulate the generated \ +// > netlist before going to test it on board. +// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed. + // Normal mode DFF negedge clk, negedge reset module \$_DFF_N_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Normal mode DFF module \$_DFF_P_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active Low Reset DFF module \$_DFF_PN0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active High Reset DFF module \$_DFF_PP0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire R_i = ~ R; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire E_i = ~ E; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); endmodule // Input buffer map diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v index 634cec789..b3a11272b 100644 --- a/techlibs/intel/cycloneive/arith_map.v +++ b/techlibs/intel/cycloneive/arith_map.v @@ -16,6 +16,48 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +/* TODO: Describe the following mode */ +module fa + (input a_c, + input b_c, + input cin_c, + output cout_t, + output sum_x); + + wire a_c; + wire b_c; + wire cout_t; + wire cin_c; + wire sum_x; + wire VCC; + + assign VCC = 1'b1; + + cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x), + .dataa(a_c), + .datab(b_c), + .datac(cin_c), + .datad(VCC)); + defparam syn__05_.lut_mask = 16'b1001011010010110; + defparam syn__05_.sum_lutc_input = "datac"; + + cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t), + .dataa(cin_c), + .datab(b_c), + .datac(a_c), + .datad(VCC)); + defparam syn__06_.lut_mask = 16'b1110000011100000; + defparam syn__06_.sum_lutc_input = "datac"; + +endmodule // fa + +module f_stage(); + +endmodule // f_stage + +module f_end(); + +endmodule // f_end module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); parameter A_SIGNED = 0; @@ -41,8 +83,13 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH:0] C = {CO, CI}; - cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); - genvar i; + fa f0 (.a_c(AA[0]), + .b_c(BB[0]), + .cin_c(C[0]), + .cout_t(C0[1]), + .sum_x(Y[0])); + + genvar i; generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i])); end endgenerate diff --git a/techlibs/intel/cycloneive/cells_map.v b/techlibs/intel/cycloneive/cells_map.v index bf87f5525..abeb92eef 100644 --- a/techlibs/intel/cycloneive/cells_map.v +++ b/techlibs/intel/cycloneive/cells_map.v @@ -16,32 +16,43 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Intel FPGA technology mapping. User must first simulate the generated \ +// > netlist before going to test it on board. +// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed. + // Normal mode DFF negedge clk, negedge reset module \$_DFF_N_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Normal mode DFF module \$_DFF_P_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule + // Async Active Low Reset DFF module \$_DFF_PN0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active High Reset DFF module \$_DFF_PP0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire R_i = ~ R; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire E_i = ~ E; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); endmodule // Input buffer map diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v index 9fe8db2da..bd60d4e17 100644 --- a/techlibs/intel/cyclonev/cells_map.v +++ b/techlibs/intel/cyclonev/cells_map.v @@ -16,33 +16,45 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Intel FPGA technology mapping. User must first simulate the generated \ +// > netlist before going to test it on board. +// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed. +// 2) Cyclone V 7-input LUT function was wrong implemented. Removed abc option to map this function \ +// and added the explanation in this file instead. Such function needs to be implemented. + // Normal mode DFF negedge clk, negedge reset module \$_DFF_N_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Normal mode DFF module \$_DFF_P_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active Low Reset DFF module \$_DFF_PN0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active High Reset DFF module \$_DFF_PP0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire R_i = ~ R; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire E_i = ~ E; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); endmodule // Input buffer map @@ -61,6 +73,10 @@ module \$lut (A, Y); parameter LUT = 0; input [WIDTH-1:0] A; output Y; + wire VCC; + wire GND; + assign {VCC,GND} = {1'b1,1'b0}; + generate if (WIDTH == 1) begin assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function @@ -72,11 +88,11 @@ module \$lut (A, Y); (.combout(Y), .dataa(A[0]), .datab(A[1]), - .datac(1'b1), - .datad(1'b1), - .datae(1'b1), - .dataf(1'b1), - .datag(1'b1)); + .datac(VCC), + .datad(VCC), + .datae(VCC), + .dataf(VCC), + .datag(VCC)); end else if(WIDTH == 3) begin @@ -86,10 +102,10 @@ module \$lut (A, Y); .dataa(A[0]), .datab(A[1]), .datac(A[2]), - .datad(1'b1), - .datae(1'b1), - .dataf(1'b1), - .datag(1'b1)); + .datad(VCC), + .datae(VCC), + .dataf(VCC), + .datag(VCC)); end else if(WIDTH == 4) begin @@ -100,9 +116,9 @@ module \$lut (A, Y); .datab(A[1]), .datac(A[2]), .datad(A[3]), - .datae(1'b1), - .dataf(1'b1), - .datag(1'b1)); + .datae(VCC), + .dataf(VCC), + .datag(VCC)); end else if(WIDTH == 5) begin @@ -114,8 +130,8 @@ module \$lut (A, Y); .datac(A[2]), .datad(A[3]), .datae(A[4]), - .dataf(1'b1), - .datag(1'b1)); + .dataf(VCC), + .datag(VCC)); end else if(WIDTH == 6) begin @@ -128,21 +144,16 @@ module \$lut (A, Y); .datad(A[3]), .datae(A[4]), .dataf(A[5]), - .datag(1'b1)); + .datag(VCC)); end - else + /*else if(WIDTH == 7) begin - cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) - _TECHMAP_REPLACE_ - (.combout(Y), - .dataa(A[0]), - .datab(A[1]), - .datac(A[2]), - .datad(A[3]), - .datae(A[4]), - .dataf(A[5]), - .datag(A[6])); - end + TODO: There's not a just 7-input function on Cyclone V, see the following note: + **Extended LUT Mode** + Use extended LUT mode to implement a specific set of 7-input functions. The set must + be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs. + [source](Device Interfaces and Integration Basics for Cyclone V Devices). + end*/ else wire _TECHMAP_FAIL_ = 1; endgenerate diff --git a/techlibs/intel/max10/cells_map.v b/techlibs/intel/max10/cells_map.v index 9229fae51..6d604e072 100644 --- a/techlibs/intel/max10/cells_map.v +++ b/techlibs/intel/max10/cells_map.v @@ -16,43 +16,53 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ +// > c60k28 (Viacheslav, VT) [at] yandex [dot] com +// > Intel FPGA technology mapping. User must first simulate the generated \ +// > netlist before going to test it on board. +// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed. + // Normal mode DFF negedge clk, negedge reset module \$_DFF_N_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Normal mode DFF module \$_DFF_P_ (input D, C, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active Low Reset DFF module \$_DFF_PN0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + parameter power_up=1'bx; + dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule // Async Active High Reset DFF module \$_DFF_PP0_ (input D, C, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire R_i = ~ R; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); endmodule module \$__DFFE_PP0 (input D, C, E, R, output Q); parameter WYSIWYG="TRUE"; + parameter power_up=1'bx; wire E_i = ~ E; - dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); + dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); endmodule // Input buffer map module \$__inpad (input I, output O); - fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); + fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); endmodule // Output buffer map module \$__outpad (input I, output O); - fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); + fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); endmodule // LUT Map diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 9e632c861..dfed7a285 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -36,7 +36,7 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log("This command runs synthesis for Intel FPGAs.\n"); log("\n"); - log(" -family < max10 | a10gx | cyclonev | cycloneiv | cycloneive>\n"); + log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if not family argument specified.\n"); log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n"); @@ -49,6 +49,11 @@ struct SynthIntelPass : public ScriptPass { log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); log("\n"); + log(" -vpr \n"); + log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); + log(" compatible with the Quartus flow. Writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -68,7 +73,7 @@ struct SynthIntelPass : public ScriptPass { log("\n"); } - string top_opt, family_opt, vout_file; + string top_opt, family_opt, vout_file, blif_file; bool retime, flatten, nobram; virtual void clear_flags() YS_OVERRIDE @@ -76,6 +81,7 @@ struct SynthIntelPass : public ScriptPass { top_opt = "-auto-top"; family_opt = "max10"; vout_file = ""; + blif_file = ""; retime = false; flatten = true; nobram = false; @@ -101,6 +107,10 @@ struct SynthIntelPass : public ScriptPass { vout_file = args[++argidx]; continue; } + if (args[argidx] == "-vpr" && argidx+1 < args.size()) { + blif_file = args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -198,7 +208,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_luts")) { if(family_opt=="a10gx" || family_opt=="cyclonev") - run("abc -luts 2:2,3,6:5,10" + string(retime ? " -dff" : "")); + run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -lut 4" + string(retime ? " -dff" : "")); run("clean"); @@ -236,7 +246,16 @@ struct SynthIntelPass : public ScriptPass { run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s", help_mode ? "" : vout_file.c_str())); } - } + + if (check_label("vpr")) + { + if (!blif_file.empty() || help_mode) + { + run(stringf("opt_clean -purge")); + run(stringf("write_blif %s", help_mode ? "" : blif_file.c_str())); + } + } + } } SynthIntelPass; PRIVATE_NAMESPACE_END From 25a864fc7344756e1b2de7bcc3f446ab84e410a3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Apr 2018 17:28:07 +0200 Subject: [PATCH 028/184] Fixed -stbv handling in SMT2 back-end --- backends/smt2/smt2.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 2fb6d4da9..ca1ceacc7 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -766,7 +766,7 @@ struct Smt2Worker if (statebv) makebits(stringf("%s_h %s", get_id(module), get_id(cell->name)), mod_stbv_width.at(cell->type)); - if (statedt) + else if (statedt) dtmembers.push_back(stringf(" (|%s_h %s| |%s_s|)\n", get_id(module), get_id(cell->name), get_id(cell->type))); else From 4d6af2969ccaf5f235fffdc8f89bc5e91fff5962 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Apr 2018 18:12:27 +0200 Subject: [PATCH 029/184] Add smtio.py support for parsing SMT2 (_ bvX n) syntax for BitVec constants Signed-off-by: Clifford Wolf --- backends/smt2/smtio.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index bf72e8916..1a8d2484c 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -737,6 +737,9 @@ class SmtIo: return h def bv2bin(self, v): + if type(v) is list and len(v) == 3 and v[0] == "_" and v[1].startswith("bv"): + x, n = int(v[1][2:]), int(v[2]) + return "".join("1" if (x & (1 << i)) else "0" for i in range(n-1, -1, -1)) if v == "true": return "1" if v == "false": return "0" if v.startswith("#b"): From 4a65b823db319920b236e4a5b35b3eef6b889c70 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 4 Apr 2018 19:27:33 +0200 Subject: [PATCH 030/184] Create issue_template.md --- .github/issue_template.md | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 .github/issue_template.md diff --git a/.github/issue_template.md b/.github/issue_template.md new file mode 100644 index 000000000..24e91a4e7 --- /dev/null +++ b/.github/issue_template.md @@ -0,0 +1,16 @@ +## Steps to reproduce the issue + +*Provide instructions for reproducing the issue. Make sure to include +all neccessary source files. (You can simply drag&drop a .zip file into +the issue editor.)* + +## Expected behavior + +*Please describe the behavior you would have expected from the tool.* + +## Actual behavior + +*Please describe how the behavior you see differs from the expected behavior.* + +**Important Note:** Nobody will be able to help you and/or fix the issue if you +do not provide sufficient information for reproducing the problem. From 705c366a91aab577858d9f45f1ebad28b8db1523 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 5 Apr 2018 11:01:32 +0200 Subject: [PATCH 031/184] Added missing dont_use handling for SR FFs to dfflibmap Signed-off-by: Clifford Wolf --- passes/techmap/dfflibmap.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 4cb1489a8..5ccb770c4 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -240,6 +240,10 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo if (cell->id != "cell" || cell->args.size() != 1) continue; + LibertyAst *dn = cell->find("dont_use"); + if (dn != NULL && dn->value == "true") + continue; + LibertyAst *ff = cell->find("ff"); if (ff == NULL) continue; From 0c404b1f6345088c97d54c851d77969a2f33b25d Mon Sep 17 00:00:00 2001 From: makaimann Date: Thu, 5 Apr 2018 17:38:08 -0700 Subject: [PATCH 032/184] Set RAM runtime flags for Verific frontend --- frontends/verific/verific.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 793e296f4..c72f513cb 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1632,6 +1632,9 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("db_preserve_user_nets", 1); RuntimeFlags::SetVar("db_allow_external_nets", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); + RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); + RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); + RuntimeFlags::SetVar("db_infer_wide_operators", 1); veri_file::DefineCmdLineMacro("VERIFIC"); veri_file::DefineCmdLineMacro("SYNTHESIS"); From ab8db2c168ed2177146ec744f6397a3a9951d7cc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 6 Apr 2018 14:10:57 +0200 Subject: [PATCH 033/184] Add "verific -autocover" Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 19 +++++++++++++++---- frontends/verific/verific.h | 3 ++- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c72f513cb..d68b81c8b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -99,9 +99,9 @@ string get_full_netlist_name(Netlist *nl) // ================================================================== -VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific) : +VerificImporter::VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover) : mode_gates(mode_gates), mode_keep(mode_keep), mode_nosva(mode_nosva), - mode_names(mode_names), mode_verific(mode_verific) + mode_names(mode_names), mode_verific(mode_verific), mode_autocover(mode_autocover) { } @@ -1279,8 +1279,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (!mode_nosva) { - for (auto inst : sva_asserts) + for (auto inst : sva_asserts) { + if (mode_autocover) + verific_import_sva_cover(this, inst); verific_import_sva_assert(this, inst); + } for (auto inst : sva_assumes) verific_import_sva_assume(this, inst); @@ -1594,6 +1597,9 @@ struct VerificPass : public Pass { log(" -extnets\n"); log(" Resolve references to external nets by adding module ports as needed.\n"); log("\n"); + log(" -autocover\n"); + log(" Generate automatic cover statements for all asserts\n"); + log("\n"); log(" -v, -vv\n"); log(" Verbose log messages. (-vv is even more verbose than -v.)\n"); log("\n"); @@ -1746,6 +1752,7 @@ struct VerificPass : public Pass { std::set nl_todo, nl_done; bool mode_all = false, mode_gates = false, mode_keep = false; bool mode_nosva = false, mode_names = false, mode_verific = false; + bool mode_autocover = false; bool flatten = false, extnets = false; string dumpfile; @@ -1778,6 +1785,10 @@ struct VerificPass : public Pass { mode_names = true; continue; } + if (args[argidx] == "-autocover") { + mode_autocover = true; + continue; + } if (args[argidx] == "-V") { mode_verific = true; continue; @@ -1930,7 +1941,7 @@ struct VerificPass : public Pass { Netlist *nl = *nl_todo.begin(); if (nl_done.count(nl) == 0) { VerificImporter importer(mode_gates, mode_keep, mode_nosva, - mode_names, mode_verific); + mode_names, mode_verific, mode_autocover); importer.import_netlist(design, nl, nl_todo); } nl_todo.erase(nl); diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 9e3e39695..2dd688e0d 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -67,8 +67,9 @@ struct VerificImporter std::map sva_posedge_map; bool mode_gates, mode_keep, mode_nosva, mode_names, mode_verific; + bool mode_autocover; - VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific); + VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names, bool mode_verific, bool mode_autocover); RTLIL::SigBit net_map_at(Verific::Net *net); From 278685b08469a94c133acff92ddf8fb32c4368f9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 6 Apr 2018 14:19:55 +0200 Subject: [PATCH 034/184] Add Verific anyseq/anyconst/allseq/allconst attribute support Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 38 ++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d68b81c8b..25af54e03 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -786,8 +786,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se module->fixup_ports(); dict init_nets; - pool anyconst_nets; - pool anyseq_nets; + pool anyconst_nets, anyseq_nets; + pool allconst_nets, allseq_nets; FOREACH_NET_OF_NETLIST(nl, mi, net) { @@ -862,12 +862,30 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se const char *rand_const_attr = net->GetAttValue(" rand_const"); const char *rand_attr = net->GetAttValue(" rand"); + const char *anyconst_attr = net->GetAttValue("anyconst"); + const char *anyseq_attr = net->GetAttValue("anyseq"); + + const char *allconst_attr = net->GetAttValue("allconst"); + const char *allseq_attr = net->GetAttValue("allseq"); + if (rand_const_attr != nullptr && !strcmp(rand_const_attr, "1")) anyconst_nets.insert(net); else if (rand_attr != nullptr && !strcmp(rand_attr, "1")) anyseq_nets.insert(net); + else if (anyconst_attr != nullptr && !strcmp(anyconst_attr, "1")) + anyconst_nets.insert(net); + + else if (anyseq_attr != nullptr && !strcmp(anyseq_attr, "1")) + anyseq_nets.insert(net); + + else if (allconst_attr != nullptr && !strcmp(allconst_attr, "1")) + allconst_nets.insert(net); + + else if (allseq_attr != nullptr && !strcmp(allseq_attr, "1")) + allseq_nets.insert(net); + if (net_map.count(net)) { if (verific_verbose) log(" skipping net %s.\n", net->Name()); @@ -951,6 +969,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se SigSpec anyconst_sig; SigSpec anyseq_sig; + SigSpec allconst_sig; + SigSpec allseq_sig; for (int i = netbus->RightIndex();; i += netbus->IsUp() ? -1 : +1) { net = netbus->ElementAtIndex(i); @@ -962,6 +982,14 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se anyseq_sig.append(net_map_at(net)); anyseq_nets.erase(net); } + if (net != nullptr && allconst_nets.count(net)) { + allconst_sig.append(net_map_at(net)); + allconst_nets.erase(net); + } + if (net != nullptr && allseq_nets.count(net)) { + allseq_sig.append(net_map_at(net)); + allseq_nets.erase(net); + } if (i == netbus->LeftIndex()) break; } @@ -971,6 +999,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (GetSize(anyseq_sig)) module->connect(anyseq_sig, module->Anyseq(NEW_ID, GetSize(anyseq_sig))); + + if (GetSize(allconst_sig)) + module->connect(allconst_sig, module->Allconst(NEW_ID, GetSize(allconst_sig))); + + if (GetSize(allseq_sig)) + module->connect(allseq_sig, module->Allseq(NEW_ID, GetSize(allseq_sig))); } for (auto it : init_nets) From 5ea2c53604aefeeaf43a638fe3c86813e947dc37 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 6 Apr 2018 14:35:11 +0200 Subject: [PATCH 035/184] Add read_verilog anyseq/anyconst/allseq/allconst attribute support Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_parser.y | 34 +++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 3dd54f532..47a5ddfa5 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -933,11 +933,43 @@ wire_name_list: wire_name_and_opt_assign: wire_name { - if (current_wire_rand) { + bool attr_anyconst = false; + bool attr_anyseq = false; + bool attr_allconst = false; + bool attr_allseq = false; + if (ast_stack.back()->children.back()->get_bool_attribute("\\anyconst")) { + delete ast_stack.back()->children.back()->attributes.at("\\anyconst"); + ast_stack.back()->children.back()->attributes.erase("\\anyconst"); + attr_anyconst = true; + } + if (ast_stack.back()->children.back()->get_bool_attribute("\\anyseq")) { + delete ast_stack.back()->children.back()->attributes.at("\\anyseq"); + ast_stack.back()->children.back()->attributes.erase("\\anyseq"); + attr_anyseq = true; + } + if (ast_stack.back()->children.back()->get_bool_attribute("\\allconst")) { + delete ast_stack.back()->children.back()->attributes.at("\\allconst"); + ast_stack.back()->children.back()->attributes.erase("\\allconst"); + attr_allconst = true; + } + if (ast_stack.back()->children.back()->get_bool_attribute("\\allseq")) { + delete ast_stack.back()->children.back()->attributes.at("\\allseq"); + ast_stack.back()->children.back()->attributes.erase("\\allseq"); + attr_allseq = true; + } + if (current_wire_rand || attr_anyconst || attr_anyseq || attr_allconst || attr_allseq) { AstNode *wire = new AstNode(AST_IDENTIFIER); AstNode *fcall = new AstNode(AST_FCALL); wire->str = ast_stack.back()->children.back()->str; fcall->str = current_wire_const ? "\\$anyconst" : "\\$anyseq"; + if (attr_anyconst) + fcall->str = "\\$anyconst"; + if (attr_anyseq) + fcall->str = "\\$anyseq"; + if (attr_allconst) + fcall->str = "\\$allconst"; + if (attr_allseq) + fcall->str = "\\$allseq"; fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall)); } From 035f778121c179e0712e6c81f19195d0ab2c2f35 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 6 Apr 2018 14:37:43 +0200 Subject: [PATCH 036/184] Add documentation for anyconst/anyseq/allconst/allseq attribute Signed-off-by: Clifford Wolf --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 514d8e2f7..2a7a3b6ee 100644 --- a/README.md +++ b/README.md @@ -402,6 +402,10 @@ Non-standard or SystemVerilog features for formal verification statements it is sufficient if just one ``$allconst/$allseq`` value triggers the property (similar to ``$anyconst/$anyseq``). +- Wires/registers decalred using the ``anyconst/anyseq/allconst/allseq`` attribute + (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven + by a ``$anyconst/$anyseq/$allconst/$allseq`` function. + - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are supported in any clocked block. From 0ac768f9df66d010bfc9ac264b1a3228f985a994 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 6 Apr 2018 21:23:47 +0200 Subject: [PATCH 037/184] Fix handling of $global_clocking in Verific Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 25af54e03..8e76d8949 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -123,8 +123,11 @@ void VerificImporter::import_attributes(dict &att attributes["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile())); // FIXME: Parse numeric attributes - FOREACH_ATTRIBUTE(obj, mi, attr) + FOREACH_ATTRIBUTE(obj, mi, attr) { + if (attr->Key()[0] == ' ' || attr->Value() == nullptr) + continue; attributes[RTLIL::escape_id(attr->Key())] = RTLIL::Const(std::string(attr->Value())); + } } RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst) @@ -1955,6 +1958,9 @@ struct VerificPass : public Pass { #endif } + if (!verific_error_msg.empty()) + goto check_error; + if (flatten) { for (auto nl : nl_todo) nl->Flatten(); From 617c60cea67f51c6208be47377978a58e010e8c8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 7 Apr 2018 18:38:42 +0200 Subject: [PATCH 038/184] Add PRIM_HDL_ASSERTION support to Verific importer Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8e76d8949..ee09c7523 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1258,11 +1258,27 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se continue; } + if (inst->Type() == PRIM_HDL_ASSERTION) + { + SigBit cond = net_map_at(inst->GetInput()); + + if (verific_verbose) + log(" assert condition %s.\n", log_signal(cond)); + + const char *assume_attr = nullptr; // inst->GetAttValue("assume"); + + Cell *cell = nullptr; + if (assume_attr != nullptr && !strcmp(assume_attr, "1")) + cell = module->addAssume(NEW_ID, cond, State::S1); + else + cell = module->addAssert(NEW_ID, cond, State::S1); + + import_attributes(cell->attributes, inst); + continue; + } + if (inst->IsPrimitive()) { - if (inst->Type() == PRIM_HDL_ASSERTION) - continue; - if (!mode_keep) log_error("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name()); From 2f0ecff71cd0ddb6e4ac3cc85950f4d504645b64 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Apr 2018 14:02:57 +0200 Subject: [PATCH 039/184] Improve Makefile error handling for when abc/ is a hg working copy Signed-off-by: Clifford Wolf --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index 0b8af9f8f..025bfd536 100644 --- a/Makefile +++ b/Makefile @@ -442,6 +442,9 @@ yosys-config: misc/yosys-config.in abc/abc-$(ABCREV)$(EXE): $(P) ifneq ($(ABCREV),default) + $(Q) if test -d abc/.hg; then \ + echo 'REEBE: NOP qverpgbel vf n ut jbexvat pbcl! Erzbir nop/ naq er-eha "znxr".' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \ + fi $(Q) if ( cd abc 2> /dev/null && ! git diff-index --quiet HEAD; ); then \ echo 'REEBE: NOP pbagnvaf ybpny zbqvsvpngvbaf! Frg NOPERI=qrsnhyg va Lbflf Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \ fi From 66ffc99695107808bd5fe0c8d09cf386dcb269fd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 12 Apr 2018 14:28:28 +0200 Subject: [PATCH 040/184] Allow "property" in immediate assertions Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_parser.y | 41 ++++++++++++++++-------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 47a5ddfa5..ef4e03a1a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1236,39 +1236,42 @@ opt_label: $$ = NULL; }; +opt_property: + TOK_PROPERTY | /* empty */; + assert: - TOK_ASSERT '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $3)); + TOK_ASSERT opt_property '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4)); } | - TOK_ASSUME '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3)); + TOK_ASSUME opt_property '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4)); } | - TOK_ASSERT '(' TOK_EVENTUALLY expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $4)); + TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5)); } | - TOK_ASSUME '(' TOK_EVENTUALLY expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4)); + TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5)); } | - TOK_COVER '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_COVER, $3)); + TOK_COVER opt_property '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4)); } | - TOK_COVER '(' ')' ';' { + TOK_COVER opt_property '(' ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false))); } | TOK_COVER ';' { ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false))); } | - TOK_RESTRICT '(' expr ')' ';' { - if (norestrict_mode) - delete $3; - else - ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3)); - } | - TOK_RESTRICT '(' TOK_EVENTUALLY expr ')' ';' { + TOK_RESTRICT opt_property '(' expr ')' ';' { if (norestrict_mode) delete $4; else - ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4)); + ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4)); + } | + TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' { + if (norestrict_mode) + delete $5; + else + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5)); }; assert_property: From 2d7f3123f0c74cafcacc18f25e14cd8bba703b4e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 13 Apr 2018 11:52:28 +0200 Subject: [PATCH 041/184] Add statement labels for immediate assertions Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_parser.y | 43 ++++++++++++++++-------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index ef4e03a1a..e803d8072 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1239,39 +1239,42 @@ opt_label: opt_property: TOK_PROPERTY | /* empty */; +opt_stmt_label: + TOK_ID ':' | /* empty */; + assert: - TOK_ASSERT opt_property '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4)); + opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5)); } | - TOK_ASSUME opt_property '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4)); + opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5)); } | - TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5)); + opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6)); } | - TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5)); + opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6)); } | - TOK_COVER opt_property '(' expr ')' ';' { - ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4)); + opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' { + ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5)); } | - TOK_COVER opt_property '(' ')' ';' { + opt_stmt_label TOK_COVER opt_property '(' ')' ';' { ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false))); } | - TOK_COVER ';' { + opt_stmt_label TOK_COVER ';' { ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false))); } | - TOK_RESTRICT opt_property '(' expr ')' ';' { - if (norestrict_mode) - delete $4; - else - ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4)); - } | - TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' { + opt_stmt_label TOK_RESTRICT opt_property '(' expr ')' ';' { if (norestrict_mode) delete $5; else - ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5)); + ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5)); + } | + opt_stmt_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' { + if (norestrict_mode) + delete $6; + else + ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6)); }; assert_property: From 5ca91ca019d5df43fbe81197c26c5c39bda63b82 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 15 Apr 2018 14:07:21 +0200 Subject: [PATCH 042/184] Add "write_blif -inames -iattr" Signed-off-by: Clifford Wolf --- backends/blif/blif.cc | 68 +++++++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 22 deletions(-) diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index f9230a1e6..e4509e0d0 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -38,8 +38,10 @@ struct BlifDumperConfig bool impltf_mode; bool gates_mode; bool cname_mode; + bool iname_mode; bool param_mode; bool attr_mode; + bool iattr_mode; bool blackbox_mode; bool noalias_mode; @@ -48,7 +50,8 @@ struct BlifDumperConfig std::string true_type, true_out, false_type, false_out, undef_type, undef_out; BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false), - cname_mode(false), param_mode(false), attr_mode(false), blackbox_mode(false), noalias_mode(false) { } + cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false), + blackbox_mode(false), noalias_mode(false) { } }; struct BlifDumper @@ -240,118 +243,118 @@ struct BlifDumper if (!config->icells_mode && cell->type == "$_NOT_") { f << stringf(".names %s %s\n0 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_AND_") { f << stringf(".names %s %s %s\n11 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_OR_") { f << stringf(".names %s %s %s\n1- 1\n-1 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_XOR_") { f << stringf(".names %s %s %s\n10 1\n01 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_NAND_") { f << stringf(".names %s %s %s\n0- 1\n-0 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_NOR_") { f << stringf(".names %s %s %s\n00 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_XNOR_") { f << stringf(".names %s %s %s\n11 1\n00 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_ANDNOT_") { f << stringf(".names %s %s %s\n10 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_ORNOT_") { f << stringf(".names %s %s %s\n1- 1\n-0 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_AOI3_") { f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_OAI3_") { f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_AOI4_") { f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_OAI4_") { f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_MUX_") { f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n", cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_FF_") { f << stringf(".latch %s %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr_init(cell->getPort("\\Q"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_DFF_N_") { f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_DFF_P_") { f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_DLATCH_N_") { f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$_DLATCH_P_") { f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q"))); - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$lut") { @@ -373,7 +376,7 @@ struct BlifDumper } f << " 1\n"; } - continue; + goto internal_cell; } if (!config->icells_mode && cell->type == "$sop") { @@ -401,7 +404,7 @@ struct BlifDumper } f << " 1\n"; } - continue; + goto internal_cell; } f << stringf(".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type)); @@ -421,6 +424,14 @@ struct BlifDumper dump_params(".attr", cell->attributes); if (config->param_mode) dump_params(".param", cell->parameters); + + if (0) { + internal_cell: + if (config->iname_mode) + f << stringf(".cname %s\n", cstr(cell->name)); + if (config->iattr_mode) + dump_params(".attr", cell->attributes); + } } for (auto &conn : module->connections()) @@ -511,6 +522,11 @@ struct BlifBackend : public Backend { log(" -cname\n"); log(" use the non-standard .cname statement to write cell names\n"); log("\n"); + log(" -iname, -iattr\n"); + log(" enable -cname and -attr functionality for .names statements\n"); + log(" (the .cname and .attr statements will be included in the BLIF\n"); + log(" output after the truth table for the .names statement)\n"); + log("\n"); log(" -blackbox\n"); log(" write blackbox cells with .blackbox statement.\n"); log("\n"); @@ -587,6 +603,14 @@ struct BlifBackend : public Backend { config.attr_mode = true; continue; } + if (args[argidx] == "-iname") { + config.iname_mode = true; + continue; + } + if (args[argidx] == "-iattr") { + config.iattr_mode = true; + continue; + } if (args[argidx] == "-blackbox") { config.blackbox_mode = true; continue; From 81a457c4a68937f8edb4c48ca5a5de86b5c05769 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 16 Apr 2018 20:44:26 +0200 Subject: [PATCH 043/184] Add "synth_ice40 -nodffe" Signed-off-by: Clifford Wolf --- techlibs/ice40/synth_ice40.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 0bb0fb139..42873305e 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -62,6 +62,9 @@ struct SynthIce40Pass : public ScriptPass log(" -nocarry\n"); log(" do not use SB_CARRY cells in output netlist\n"); log("\n"); + log(" -nodffe\n"); + log(" do not use SB_DFFE* cells in output netlist\n"); + log("\n"); log(" -nobram\n"); log(" do not use SB_RAM40_4K* cells in output netlist\n"); log("\n"); @@ -79,7 +82,7 @@ struct SynthIce40Pass : public ScriptPass } string top_opt, blif_file, edif_file; - bool nocarry, nobram, flatten, retime, abc2, vpr; + bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr; virtual void clear_flags() YS_OVERRIDE { @@ -87,6 +90,7 @@ struct SynthIce40Pass : public ScriptPass blif_file = ""; edif_file = ""; nocarry = false; + nodffe = false; nobram = false; flatten = true; retime = false; @@ -138,6 +142,10 @@ struct SynthIce40Pass : public ScriptPass nocarry = true; continue; } + if (args[argidx] == "-nodffe") { + nodffe = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -209,7 +217,8 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_ffs")) { run("dffsr2dff"); - run("dff2dffe -direct-match $_DFF_*"); + if (!nodffe) + run("dff2dffe -direct-match $_DFF_*"); run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); From ca39e493ba78e7a4eaf3f0876321f892cce20f65 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 15 Apr 2018 16:05:52 -0700 Subject: [PATCH 044/184] synth_ice40: Rework the vpr blif output slightly. --- techlibs/ice40/synth_ice40.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 42873305e..10a1d600b 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -260,13 +260,17 @@ struct SynthIce40Pass : public ScriptPass if (!blif_file.empty() || help_mode) { if (vpr || help_mode) { run(stringf("opt_clean -purge"), - " (vpr mode)"); - run(stringf("write_blif %s", help_mode ? "" : blif_file.c_str()), - " (vpr mode)"); + " " + " (vpr mode)"); + run(stringf("write_blif -attr -cname -conn -param %s", + help_mode ? "" : blif_file.c_str()), + " (vpr mode)"); } if (!vpr) run(stringf("write_blif -gates -attr -param %s", - help_mode ? "" : blif_file.c_str()), "(non-vpr mode)"); + help_mode ? "" : blif_file.c_str()), + " " + " (non-vpr mode)"); } } From d6bdefd2e93ad25fd63103d4b76a5573debc6d03 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 18 Apr 2018 16:48:05 -0700 Subject: [PATCH 045/184] Improving vpr output support. * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. --- techlibs/ice40/cells_map.v | 2 +- techlibs/ice40/synth_ice40.cc | 6 +++--- techlibs/xilinx/cells_map.v | 2 ++ techlibs/xilinx/synth_xilinx.cc | 37 ++++++++++++++++++++++++++++++--- 4 files changed, 40 insertions(+), 7 deletions(-) diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 6550b75cf..d0ddfd02e 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -27,7 +27,7 @@ module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ ( module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule -`ifndef NO_SB_LUT4 +`ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 10a1d600b..177581d53 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -219,7 +219,7 @@ struct SynthIce40Pass : public ScriptPass run("dffsr2dff"); if (!nodffe) run("dff2dffe -direct-match $_DFF_*"); - run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v"); + run("techmap -D NO_LUT -map +/ice40/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); run("ice40_ffinit"); @@ -241,9 +241,9 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_cells")) { if (vpr) - run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v"); + run("techmap -D NO_LUT -map +/ice40/cells_map.v"); else - run("techmap -map +/ice40/cells_map.v", "(with -D NO_SB_LUT4 in vpr mode)"); + run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)"); run("clean"); } diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 8e5a83ce5..0771be0b9 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -15,6 +15,7 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED( module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule +`ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; @@ -82,3 +83,4 @@ module \$lut (A, Y); end endgenerate endmodule +`endif diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b60295ac0..1bc61daef 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -34,8 +34,10 @@ bool check_label(bool &active, std::string run_from, std::string run_to, std::st return active; } -struct SynthXilinxPass : public Pass { +struct SynthXilinxPass : public Pass +{ SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { } + virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -53,6 +55,14 @@ struct SynthXilinxPass : public Pass { log(" write the design to the specified edif file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); + log(" -blif \n"); + log(" write the design to the specified BLIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -vpr\n"); + log(" generate an output netlist (and BLIF file) suitable for VPR\n"); + log(" (this feature is experimental and incomplete)\n"); + log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -102,7 +112,7 @@ struct SynthXilinxPass : public Pass { log(" clean\n"); log("\n"); log(" map_cells:\n"); - log(" techmap -map +/xilinx/cells_map.v\n"); + log(" techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT\n"); log(" clean\n"); log("\n"); @@ -114,14 +124,19 @@ struct SynthXilinxPass : public Pass { log(" edif: (only if -edif)\n"); log(" write_edif \n"); log("\n"); + log(" blif: (only if -blif)\n"); + log(" write_blif \n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { std::string top_opt = "-auto-top"; std::string edif_file; + std::string blif_file; std::string run_from, run_to; bool flatten = false; bool retime = false; + bool vpr = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -134,6 +149,10 @@ struct SynthXilinxPass : public Pass { edif_file = args[++argidx]; continue; } + if (args[argidx] == "-blif" && argidx+1 < args.size()) { + blif_file = args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -150,6 +169,10 @@ struct SynthXilinxPass : public Pass { retime = true; continue; } + if (args[argidx] == "-vpr") { + vpr = true; + continue; + } break; } extra_args(args, argidx, design); @@ -212,7 +235,10 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_cells")) { - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + if (vpr) + Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v"); + else + Pass::call(design, "techmap -map +/xilinx/cells_map.v"); Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT"); Pass::call(design, "clean"); } @@ -229,6 +255,11 @@ struct SynthXilinxPass : public Pass { if (!edif_file.empty()) Pass::call(design, stringf("write_edif %s", edif_file.c_str())); } + if (check_label(active, run_from, run_to, "blif")) + { + if (!blif_file.empty()) + Pass::call(design, stringf("write_blif %s", edif_file.c_str())); + } log_pop(); } From d9a2b43014696fe07c96c822b1009503d052ffc4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Apr 2018 16:03:26 +0200 Subject: [PATCH 046/184] Add $dlatch support to write_verilog Signed-off-by: Clifford Wolf --- backends/verilog/verilog_backend.cc | 38 +++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index bdf705056..b50dc12af 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -897,6 +897,42 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$dlatch") + { + RTLIL::SigSpec sig_en; + bool pol_en = false; + + sig_en = cell->getPort("\\EN"); + pol_en = cell->parameters["\\EN_POLARITY"].as_bool(); + + std::string reg_name = cellname(cell); + bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); + + if (!out_is_reg_wire) { + f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); + dump_reg_init(f, cell->getPort("\\Q")); + f << ";\n"; + } + + f << stringf("%s" "always @*\n", indent.c_str()); + + f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!"); + dump_sigspec(f, sig_en); + f << stringf(")\n"); + + f << stringf("%s" " %s = ", indent.c_str(), reg_name.c_str()); + dump_cell_expr_port(f, cell, "D", false); + f << stringf(";\n"); + + if (!out_is_reg_wire) { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Q")); + f << stringf(" = %s;\n", reg_name.c_str()); + } + + return true; + } + if (cell->type == "$mem") { RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string(); @@ -1537,6 +1573,8 @@ struct VerilogBackend : public Backend { reg_ct.insert("$dff"); reg_ct.insert("$adff"); + reg_ct.insert("$dffe"); + reg_ct.insert("$dlatch"); reg_ct.insert("$_DFF_N_"); reg_ct.insert("$_DFF_P_"); From b4c1d3084ffb2b0a5ec2207cb46004fd89cdae80 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Apr 2018 13:02:56 +0200 Subject: [PATCH 047/184] Add "synth_intel --noiopads" Signed-off-by: Clifford Wolf --- techlibs/intel/synth_intel.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index dfed7a285..c51949bd4 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -59,6 +59,9 @@ struct SynthIntelPass : public ScriptPass { log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); + log(" -noiopads\n"); + log(" do not use altsyncram cells in output netlist\n"); + log("\n"); log(" -nobram\n"); log(" do not use altsyncram cells in output netlist\n"); log("\n"); @@ -74,7 +77,7 @@ struct SynthIntelPass : public ScriptPass { } string top_opt, family_opt, vout_file, blif_file; - bool retime, flatten, nobram; + bool retime, flatten, nobram, noiopads; virtual void clear_flags() YS_OVERRIDE { @@ -85,6 +88,7 @@ struct SynthIntelPass : public ScriptPass { retime = false; flatten = true; nobram = false; + noiopads = false; } virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -119,6 +123,10 @@ struct SynthIntelPass : public ScriptPass { run_to = args[argidx].substr(pos+1); continue; } + if (args[argidx] == "-noiopads") { + noiopads = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -216,7 +224,8 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { - run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I"); + if (!noiopads) + run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); if(family_opt=="max10") run("techmap -map +/intel/max10/cells_map.v"); else if(family_opt=="a10gx") From ea3ff6f59c9d406d67bc97cb7a8a884c60028275 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 30 Apr 2018 19:50:34 +0200 Subject: [PATCH 048/184] Update ABC to git rev f23ea8e Signed-off-by: Clifford Wolf --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 025bfd536..9cdb8d2db 100644 --- a/Makefile +++ b/Makefile @@ -102,7 +102,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = a2d59be +ABCREV = f23ea8e ABCPULL = 1 ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 From e060375f23d56b4e330a946d5a626f0163499618 Mon Sep 17 00:00:00 2001 From: Dan Gisselquist Date: Thu, 3 May 2018 12:35:01 +0200 Subject: [PATCH 049/184] Support more character literals --- frontends/verilog/verilog_lexer.l | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 32d7738cf..d12c9ee4e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -241,10 +241,18 @@ YOSYS_NAMESPACE_END while (yystr[i]) { if (yystr[i] == '\\' && yystr[i + 1]) { i++; - if (yystr[i] == 'n') + if (yystr[i] == 'a') + yystr[i] = '\a'; + else if (yystr[i] == 'f') + yystr[i] = '\f'; + else if (yystr[i] == 'n') yystr[i] = '\n'; + else if (yystr[i] == 'r') + yystr[i] = '\r'; else if (yystr[i] == 't') yystr[i] = '\t'; + else if (yystr[i] == 'v') + yystr[i] = '\v'; else if ('0' <= yystr[i] && yystr[i] <= '7') { yystr[i] = yystr[i] - '0'; if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { From a572b495387743a58111e7264917a497faa17ebf Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 3 May 2018 15:25:59 +0200 Subject: [PATCH 050/184] Replace -ignore_redef with -[no]overwrite Signed-off-by: Clifford Wolf --- frontends/ast/ast.cc | 18 ++++++++++----- frontends/ast/ast.h | 2 +- frontends/liberty/liberty.cc | 32 +++++++++++++++++++++------ frontends/verilog/verilog_frontend.cc | 23 ++++++++++++++----- passes/techmap/techmap.cc | 4 ++-- 5 files changed, 58 insertions(+), 21 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 037a9f3ee..999202b47 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1003,7 +1003,7 @@ static AstModule* process_module(AstNode *ast, bool defer) // create AstModule instances for all modules in the AST tree and add them to 'design' void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, - bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire) + bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) { current_ast = ast; flag_dump_ast1 = dump_ast1; @@ -1042,12 +1042,20 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump (*it)->str = "$abstract" + (*it)->str; if (design->has((*it)->str)) { - if (!ignore_redef) + RTLIL::Module *existing_mod = design->module((*it)->str); + if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { log_error("Re-definition of module `%s' at %s:%d!\n", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); - log("Ignoring re-definition of module `%s' at %s:%d!\n", - (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); - continue; + } else if (nooverwrite) { + log("Ignoring re-definition of module `%s' at %s:%d.\n", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + continue; + } else { + log("Replacing existing%s module `%s' at %s:%d.\n", + existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + design->remove(existing_mod); + } } design->add(process_module(*it, defer)); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index d1e2c78d1..756629aca 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -275,7 +275,7 @@ namespace AST // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, - bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); + bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index af80c2921..877b1883e 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -463,9 +463,13 @@ struct LibertyFrontend : public Frontend { log(" -lib\n"); log(" only create empty blackbox modules\n"); log("\n"); - log(" -ignore_redef\n"); + log(" -nooverwrite\n"); log(" ignore re-definitions of modules. (the default behavior is to\n"); - log(" create an error message.)\n"); + log(" create an error message if the existing module is not a blackbox\n"); + log(" module, and overwrite the existing module if it is a blackbox module.)\n"); + log("\n"); + log(" -overwrite\n"); + log(" overwrite existing modules with the same name\n"); log("\n"); log(" -ignore_miss_func\n"); log(" ignore cells with missing function specification of outputs\n"); @@ -484,7 +488,8 @@ struct LibertyFrontend : public Frontend { virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) { bool flag_lib = false; - bool flag_ignore_redef = false; + bool flag_nooverwrite = false; + bool flag_overwrite = false; bool flag_ignore_miss_func = false; bool flag_ignore_miss_dir = false; bool flag_ignore_miss_data_latch = false; @@ -499,8 +504,14 @@ struct LibertyFrontend : public Frontend { flag_lib = true; continue; } - if (arg == "-ignore_redef") { - flag_ignore_redef = true; + if (arg == "-ignore_redef" || arg == "-nooverwrite") { + flag_nooverwrite = true; + flag_overwrite = false; + continue; + } + if (arg == "-overwrite") { + flag_nooverwrite = false; + flag_overwrite = true; continue; } if (arg == "-ignore_miss_func") { @@ -537,9 +548,16 @@ struct LibertyFrontend : public Frontend { std::string cell_name = RTLIL::escape_id(cell->args.at(0)); if (design->has(cell_name)) { - if (flag_ignore_redef) + Module *existing_mod = design->module(cell_name); + if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { + log_error("Re-definition of of cell/module %s!\n", log_id(cell_name)); + } else if (flag_nooverwrite) { + log("Ignoring re-definition of module %s.\n", log_id(cell_name)); continue; - log_error("Duplicate definition of cell/module %s.\n", RTLIL::unescape_id(cell_name).c_str()); + } else { + log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name)); + design->remove(existing_mod); + } } // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str()); diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index e5917b97e..505c94619 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -137,9 +137,13 @@ struct VerilogFrontend : public Frontend { log(" -icells\n"); log(" interpret cell types starting with '$' as internal cell types\n"); log("\n"); - log(" -ignore_redef\n"); + log(" -nooverwrite\n"); log(" ignore re-definitions of modules. (the default behavior is to\n"); - log(" create an error message.)\n"); + log(" create an error message if the existing module is not a black box\n"); + log(" module, and overwrite the existing module otherwise.)\n"); + log("\n"); + log(" -overwrite\n"); + log(" overwrite existing modules with the same name\n"); log("\n"); log(" -defer\n"); log(" only read the abstract syntax tree and defer actual compilation\n"); @@ -191,7 +195,8 @@ struct VerilogFrontend : public Frontend { bool flag_nodpi = false; bool flag_noopt = false; bool flag_icells = false; - bool flag_ignore_redef = false; + bool flag_nooverwrite = false; + bool flag_overwrite = false; bool flag_defer = false; std::map defines_map; std::list include_dirs; @@ -289,8 +294,14 @@ struct VerilogFrontend : public Frontend { flag_icells = true; continue; } - if (arg == "-ignore_redef") { - flag_ignore_redef = true; + if (arg == "-ignore_redef" || arg == "-nooverwrite") { + flag_nooverwrite = true; + flag_overwrite = false; + continue; + } + if (arg == "-overwrite") { + flag_nooverwrite = false; + flag_overwrite = true; continue; } if (arg == "-defer") { @@ -370,7 +381,7 @@ struct VerilogFrontend : public Frontend { if (flag_nodpi) error_on_dpi_function(current_ast); - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 02d0d47e8..1908ae8b5 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -933,7 +933,7 @@ struct TechmapPass : public Pass { log(" -D , -I \n"); log(" this options are passed as-is to the Verilog frontend for loading the\n"); log(" map file. Note that the Verilog frontend is also called with the\n"); - log(" '-ignore_redef' option set.\n"); + log(" '-nooverwrite' option set.\n"); log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n"); @@ -1031,7 +1031,7 @@ struct TechmapPass : public Pass { simplemap_get_mappers(worker.simplemap_mappers); std::vector map_files; - std::string verilog_frontend = "verilog -ignore_redef"; + std::string verilog_frontend = "verilog -nooverwrite"; int max_iter = -1; size_t argidx; From 5c03aeac60b8f8e88367d3bbf3b13b84a54ef11b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 4 May 2018 15:27:28 +0200 Subject: [PATCH 051/184] Add "yosys -e regex" for turning warnings into errors Signed-off-by: Clifford Wolf --- kernel/driver.cc | 14 ++++++++++++-- kernel/log.cc | 10 +++++++++- kernel/log.h | 2 +- 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 3c16e5fd4..7a1dce497 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -255,9 +255,13 @@ int main(int argc, char **argv) printf(" print a warning for all log messages matching the regex.\n"); printf("\n"); printf(" -w regex\n"); - printf(" if a warning message matches the regex, it is printes as regular\n"); + printf(" if a warning message matches the regex, it is printed as regular\n"); printf(" message instead.\n"); printf("\n"); + printf(" -e regex\n"); + printf(" if a warning message matches the regex, it is printed as error\n"); + printf(" message instead and the tool terminates with a nonzero return code.\n"); + printf("\n"); printf(" -E \n"); printf(" write a Makefile dependencies file with in- and output file names\n"); printf("\n"); @@ -281,7 +285,7 @@ int main(int argc, char **argv) } int opt; - while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:D:E:")) != -1) + while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:E:")) != -1) { switch (opt) { @@ -375,6 +379,12 @@ int main(int argc, char **argv) std::regex_constants::optimize | std::regex_constants::egrep)); break; + case 'e': + log_werror_regexes.push_back(std::regex(optarg, + std::regex_constants::nosubs | + std::regex_constants::optimize | + std::regex_constants::egrep)); + break; case 'D': { auto args = split_tokens(optarg, ":"); diff --git a/kernel/log.cc b/kernel/log.cc index de564cb36..ff171f3e6 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -41,7 +41,7 @@ YOSYS_NAMESPACE_BEGIN std::vector log_files; std::vector log_streams; std::map> log_hdump; -std::vector log_warn_regexes, log_nowarn_regexes; +std::vector log_warn_regexes, log_nowarn_regexes, log_werror_regexes; std::set log_warnings; int log_warnings_count = 0; bool log_hdump_all = false; @@ -218,6 +218,10 @@ void logv_warning(const char *format, va_list ap) } else { + for (auto &re : log_werror_regexes) + if (std::regex_search(message, re)) + log_error("%s", message.c_str()); + if (log_warnings.count(message)) { log("Warning: %s", message.c_str()); @@ -256,6 +260,10 @@ void logv_warning_noprefix(const char *format, va_list ap) } else { + for (auto &re : log_werror_regexes) + if (std::regex_search(message, re)) + log_error("%s", message.c_str()); + if (log_warnings.count(message)) { log("%s", message.c_str()); diff --git a/kernel/log.h b/kernel/log.h index 90a12df36..457229c87 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -49,7 +49,7 @@ struct log_cmd_error_exception { }; extern std::vector log_files; extern std::vector log_streams; extern std::map> log_hdump; -extern std::vector log_warn_regexes, log_nowarn_regexes; +extern std::vector log_warn_regexes, log_nowarn_regexes, log_werror_regexes; extern std::set log_warnings; extern int log_warnings_count; extern bool log_hdump_all; From 145c685de03a0b5f70a3aa821ea1bd221c31d993 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 4 May 2018 21:59:31 +0200 Subject: [PATCH 052/184] Add ABC FAQ to "help abc" Signed-off-by: Clifford Wolf --- passes/techmap/abc.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index be86f642a..009ba6b97 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1388,8 +1388,12 @@ struct AbcPass : public Pass { log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n"); log("loaded into ABC before the ABC script is executed.\n"); log("\n"); - log("This pass does not operate on modules with unprocessed processes in it.\n"); - log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n"); + log("Note that this is a logic optimization pass within Yosys that is calling ABC\n"); + log("internally. This is not going to \"run ABC on your design\". It will instead run\n"); + log("ABC on logic snippets extracted from your design. You will not get any useful\n"); + log("output when passing an ABC script that writes a file. Instead write your full\n"); + log("design as BLIF file with write_blif and the load that into ABC externally if\n"); + log("you want to use ABC to convert your design into another format.\n"); log("\n"); log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("\n"); From e3575a86c525f2511902e7022893c3923ba8093e Mon Sep 17 00:00:00 2001 From: Johnny Sorocil Date: Sat, 5 May 2018 13:02:44 +0200 Subject: [PATCH 053/184] Add "#ifdef __FreeBSD__" --- kernel/driver.cc | 24 +++++++++++++++++++++--- kernel/log.cc | 6 +++--- kernel/log.h | 2 +- kernel/yosys.cc | 27 ++++++++++++++++++++++++++- passes/cmds/cover.cc | 2 +- 5 files changed, 52 insertions(+), 9 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 7a1dce497..bec872c24 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -34,12 +34,17 @@ #include #include -#ifdef __linux__ +#if defined (__linux__) || defined(__FreeBSD__) # include # include # include #endif +#ifdef __FreeBSD__ +# include +# include +#endif + #if !defined(_WIN32) || defined(__MINGW32__) # include #else @@ -510,7 +515,7 @@ int main(int argc, char **argv) #else std::string meminfo; std::string stats_divider = ", "; -# ifdef __linux__ +# if defined(__linux__) std::ifstream statm; statm.open(stringf("/proc/%lld/statm", (long long)getpid())); if (statm.is_open()) { @@ -521,6 +526,19 @@ int main(int argc, char **argv) sz_resident * (getpagesize() / 1024.0 / 1024.0)); stats_divider = "\n"; } +# elif defined(__FreeBSD__) + pid_t pid = getpid(); + int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PID, (int)pid}; + struct kinfo_proc kip; + size_t kip_len = sizeof(kip); + if (sysctl(mib, 4, &kip, &kip_len, NULL, 0) == 0) { + vm_size_t sz_total = kip.ki_size; + segsz_t sz_resident = kip.ki_rssize; + meminfo = stringf(", MEM: %.2f MB total, %.2f MB resident", + (int)sz_total / 1024.0 / 1024.0, + (int)sz_resident * (getpagesize() / 1024.0 / 1024.0)); + stats_divider = "\n"; + } # endif struct rusage ru_buffer; @@ -564,7 +582,7 @@ int main(int argc, char **argv) } } -#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) +#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE")) { string filename; diff --git a/kernel/log.cc b/kernel/log.cc index ff171f3e6..6d562b9e6 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -25,7 +25,7 @@ # include #endif -#ifdef __linux__ +#if defined(__linux__) || defined(__FreeBSD__) # include #endif @@ -392,7 +392,7 @@ void log_pop() log_flush(); } -#if defined(__linux__) && defined(YOSYS_ENABLE_PLUGINS) +#if (defined(__linux__) || defined(__FreeBSD__)) && defined(YOSYS_ENABLE_PLUGINS) void log_backtrace(const char *prefix, int levels) { if (levels <= 0) return; @@ -587,7 +587,7 @@ void log_wire(RTLIL::Wire *wire, std::string indent) // --------------------------------------------------- // This is the magic behind the code coverage counters // --------------------------------------------------- -#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) +#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) dict> extra_coverage_data; diff --git a/kernel/log.h b/kernel/log.h index 457229c87..a2aacfd4d 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -114,7 +114,7 @@ static inline void log_assert_worker(bool cond, const char *expr, const char *fi // This is the magic behind the code coverage counters // --------------------------------------------------- -#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) +#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) #define cover(_id) do { \ static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \ diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 49d644548..aa5901271 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -46,10 +46,15 @@ # include # include # include +# include # include # include #endif +#ifdef __FreeBSD__ +# include +#endif + #include #include @@ -72,7 +77,7 @@ std::vector memhasher_store; void memhasher_on() { -#ifdef __linux__ +#if defined(__linux__) || defined(__FreeBSD__) memhasher_rng += time(NULL) << 16 ^ getpid(); #endif memhasher_store.resize(0x10000); @@ -667,6 +672,26 @@ std::string proc_self_dirname() buflen--; return std::string(path, buflen); } +#elif defined(__FreeBSD__) +std::string proc_self_dirname() +{ + int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PATHNAME, -1}; + size_t buflen; + char *buffer; + std::string path; + if (sysctl(mib, 4, NULL, &buflen, NULL, 0) != 0) + log_error("sysctl failed: %s\n", strerror(errno)); + buffer = (char*)malloc(buflen); + if (buffer == NULL) + log_error("malloc failed: %s\n", strerror(errno)); + if (sysctl(mib, 4, buffer, &buflen, NULL, 0) != 0) + log_error("sysctl failed: %s\n", strerror(errno)); + while (buflen > 0 && buffer[buflen-1] != '/') + buflen--; + path.assign(buffer, buflen); + free(buffer); + return path; +} #elif defined(__APPLE__) std::string proc_self_dirname() { diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 1475475c3..ef4f3f7d0 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -128,7 +128,7 @@ struct CoverPass : public Pass { log("\n"); } -#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) +#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) for (auto &it : get_coverage_data()) { if (!patterns.empty()) { for (auto &p : patterns) From 3e67497ec2577d4b46cc5a728420d06e66ec434c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 5 May 2018 13:58:01 +0200 Subject: [PATCH 054/184] Fix handling of zero-length SVA consecutive repetition Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 74 +++++++++++++++++++++------------ 1 file changed, 47 insertions(+), 27 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 8dc213a18..51e67ef79 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -50,11 +50,11 @@ // sequence ##[+] sequence // sequence ##[N:M] sequence // sequence ##[N:$] sequence -// sequence [*] -// sequence [+] -// sequence [*N] -// sequence [*N:M] -// sequence [*N:$] +// expression [*] +// expression [+] +// expression [*N] +// expression [*N:M] +// expression [*N:$] // sequence or sequence // sequence and sequence // expression throughout sequence @@ -1138,7 +1138,7 @@ struct VerificSvaImporter log_abort(); } - int parse_sequence(SvaFsm &fsm, int start_node, Net *net) + int parse_sequence(SvaFsm &fsm, int start_node, Net *net, int past_start_node = -1) { if (check_expression(net)) { int node = fsm.createNode(); @@ -1183,15 +1183,28 @@ struct VerificSvaImporter bool sva_inf = !strcmp(sva_high_s, "$"); int node = parse_sequence(fsm, start_node, inst->GetInput1()); + int past_node = -1; + + Net *next_net = inst->GetInput2(); + Instance *next_inst = net_to_ast_driver(next_net); + + if (next_inst != nullptr && next_inst->Type() == PRIM_SVA_CONSECUTIVE_REPEAT && sva_low > 0) { + past_node = fsm.createNode(); + log_dump(past_node); + } for (int i = 0; i < sva_low; i++) { int next_node = fsm.createNode(); fsm.createEdge(node, next_node); + if (past_node >= 0 && i == sva_low-1) + fsm.createLink(node, past_node); node = next_node; } if (sva_inf) { + if (past_node >= 0) + fsm.createLink(node, past_node); fsm.createEdge(node, node); } else @@ -1201,11 +1214,13 @@ struct VerificSvaImporter int next_node = fsm.createNode(); fsm.createEdge(node, next_node); fsm.createLink(node, next_node); + if (past_node >= 0) + fsm.createLink(node, past_node); node = next_node; } } - node = parse_sequence(fsm, node, inst->GetInput2()); + node = parse_sequence(fsm, node, inst->GetInput2(), past_node); return node; } @@ -1220,46 +1235,51 @@ struct VerificSvaImporter bool sva_inf = !strcmp(sva_high_s, "$"); Net *body_net = inst->GetInput(); - int node = fsm.createNode(start_node); - for (int i = 0; i < sva_low; i++) + bool bypass = false; + + if (sva_low == 0) { + if (past_start_node == -1) + parser_error("Possibly zero-length consecutive repeat must follow a delay of at least one cycle", inst); + bypass = true; + sva_low++; + } + + int node = fsm.createNode(start_node); + int prev_node = node; + node = parse_sequence(fsm, node, body_net); + + for (int i = 1; i < sva_low; i++) { int next_node = fsm.createNode(); + fsm.createEdge(node, next_node); - if (i == 0) - fsm.createLink(node, next_node); - else - fsm.createEdge(node, next_node); - + prev_node = node; node = parse_sequence(fsm, next_node, body_net); } if (sva_inf) { - int next_node = fsm.createNode(); - fsm.createEdge(node, next_node); - - next_node = parse_sequence(fsm, next_node, body_net); - fsm.createLink(next_node, node); + log_assert(prev_node >= 0); + fsm.createEdge(node, prev_node); } else { for (int i = sva_low; i < sva_high; i++) { int next_node = fsm.createNode(); + fsm.createEdge(node, next_node); - if (i == 0) - fsm.createLink(node, next_node); - else - fsm.createEdge(node, next_node); + prev_node = node; + node = parse_sequence(fsm, next_node, body_net); - next_node = parse_sequence(fsm, next_node, body_net); - - fsm.createLink(node, next_node); - node = next_node; + fsm.createLink(prev_node, node); } } + if (bypass) + fsm.createLink(past_start_node, node); + return node; } From 24e64016173f586233e77f4e0d70c7883f98d8f7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 5 May 2018 14:32:04 +0200 Subject: [PATCH 055/184] Further improve handling of zero-length SVA consecutive repetition Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 177 +++++++++++++++++++------------- 1 file changed, 108 insertions(+), 69 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 51e67ef79..4e440b4ca 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1138,7 +1138,98 @@ struct VerificSvaImporter log_abort(); } - int parse_sequence(SvaFsm &fsm, int start_node, Net *net, int past_start_node = -1) + bool check_zero_consecutive_repeat(Net *net) + { + Instance *inst = net_to_ast_driver(net); + + if (inst == nullptr) + return false; + + if (inst->Type() != PRIM_SVA_CONSECUTIVE_REPEAT) + return false; + + const char *sva_low_s = inst->GetAttValue("sva:low"); + int sva_low = atoi(sva_low_s); + + return sva_low == 0; + } + + int parse_consecutive_repeat(SvaFsm &fsm, int start_node, Net *net, bool add_pre_delay, bool add_post_delay) + { + Instance *inst = net_to_ast_driver(net); + + log_assert(inst->Type() == PRIM_SVA_CONSECUTIVE_REPEAT); + + const char *sva_low_s = inst->GetAttValue("sva:low"); + const char *sva_high_s = inst->GetAttValue("sva:high"); + + int sva_low = atoi(sva_low_s); + int sva_high = atoi(sva_high_s); + bool sva_inf = !strcmp(sva_high_s, "$"); + + Net *body_net = inst->GetInput(); + + if (add_pre_delay || add_post_delay) + log_assert(sva_low == 0); + + if (sva_low == 0) { + if (!add_pre_delay && !add_post_delay) + parser_error("Possibly zero-length consecutive repeat must follow or precede a delay of at least one cycle", inst); + sva_low++; + } + + int node = fsm.createNode(start_node); + start_node = node; + + if (add_pre_delay) { + node = fsm.createNode(start_node); + fsm.createEdge(start_node, node); + } + + int prev_node = node; + node = parse_sequence(fsm, node, body_net); + + for (int i = 1; i < sva_low; i++) + { + int next_node = fsm.createNode(); + fsm.createEdge(node, next_node); + + prev_node = node; + node = parse_sequence(fsm, next_node, body_net); + } + + if (sva_inf) + { + log_assert(prev_node >= 0); + fsm.createEdge(node, prev_node); + } + else + { + for (int i = sva_low; i < sva_high; i++) + { + int next_node = fsm.createNode(); + fsm.createEdge(node, next_node); + + prev_node = node; + node = parse_sequence(fsm, next_node, body_net); + + fsm.createLink(prev_node, node); + } + } + + if (add_post_delay) { + int next_node = fsm.createNode(); + fsm.createEdge(node, next_node); + node = next_node; + } + + if (add_pre_delay || add_post_delay) + fsm.createLink(start_node, node); + + return node; + } + + int parse_sequence(SvaFsm &fsm, int start_node, Net *net) { if (check_expression(net)) { int node = fsm.createNode(); @@ -1182,29 +1273,29 @@ struct VerificSvaImporter int sva_high = atoi(sva_high_s); bool sva_inf = !strcmp(sva_high_s, "$"); - int node = parse_sequence(fsm, start_node, inst->GetInput1()); - int past_node = -1; + int node = -1; + bool past_add_delay = false; - Net *next_net = inst->GetInput2(); - Instance *next_inst = net_to_ast_driver(next_net); + if (check_zero_consecutive_repeat(inst->GetInput1()) && sva_low > 0) { + node = parse_consecutive_repeat(fsm, start_node, inst->GetInput1(), false, true); + sva_low--, sva_high--; + } else { + node = parse_sequence(fsm, start_node, inst->GetInput1()); + } - if (next_inst != nullptr && next_inst->Type() == PRIM_SVA_CONSECUTIVE_REPEAT && sva_low > 0) { - past_node = fsm.createNode(); - log_dump(past_node); + if (check_zero_consecutive_repeat(inst->GetInput2()) && sva_low > 0) { + past_add_delay = true; + sva_low--, sva_high--; } for (int i = 0; i < sva_low; i++) { int next_node = fsm.createNode(); fsm.createEdge(node, next_node); - if (past_node >= 0 && i == sva_low-1) - fsm.createLink(node, past_node); node = next_node; } if (sva_inf) { - if (past_node >= 0) - fsm.createLink(node, past_node); fsm.createEdge(node, node); } else @@ -1214,73 +1305,21 @@ struct VerificSvaImporter int next_node = fsm.createNode(); fsm.createEdge(node, next_node); fsm.createLink(node, next_node); - if (past_node >= 0) - fsm.createLink(node, past_node); node = next_node; } } - node = parse_sequence(fsm, node, inst->GetInput2(), past_node); + if (past_add_delay) + node = parse_consecutive_repeat(fsm, node, inst->GetInput2(), true, false); + else + node = parse_sequence(fsm, node, inst->GetInput2()); return node; } if (inst->Type() == PRIM_SVA_CONSECUTIVE_REPEAT) { - const char *sva_low_s = inst->GetAttValue("sva:low"); - const char *sva_high_s = inst->GetAttValue("sva:high"); - - int sva_low = atoi(sva_low_s); - int sva_high = atoi(sva_high_s); - bool sva_inf = !strcmp(sva_high_s, "$"); - - Net *body_net = inst->GetInput(); - - bool bypass = false; - - if (sva_low == 0) { - if (past_start_node == -1) - parser_error("Possibly zero-length consecutive repeat must follow a delay of at least one cycle", inst); - bypass = true; - sva_low++; - } - - int node = fsm.createNode(start_node); - int prev_node = node; - node = parse_sequence(fsm, node, body_net); - - for (int i = 1; i < sva_low; i++) - { - int next_node = fsm.createNode(); - fsm.createEdge(node, next_node); - - prev_node = node; - node = parse_sequence(fsm, next_node, body_net); - } - - if (sva_inf) - { - log_assert(prev_node >= 0); - fsm.createEdge(node, prev_node); - } - else - { - for (int i = sva_low; i < sva_high; i++) - { - int next_node = fsm.createNode(); - fsm.createEdge(node, next_node); - - prev_node = node; - node = parse_sequence(fsm, next_node, body_net); - - fsm.createLink(prev_node, node); - } - } - - if (bypass) - fsm.createLink(past_start_node, node); - - return node; + return parse_consecutive_repeat(fsm, start_node, net, false, false); } if (inst->Type() == PRIM_SVA_NON_CONSECUTIVE_REPEAT || inst->Type() == PRIM_SVA_GOTO_REPEAT) From 74f2787b10bbfdc5fc485715e8d9d8b04bbae094 Mon Sep 17 00:00:00 2001 From: Johnny Sorocil Date: Sun, 6 May 2018 15:19:44 +0200 Subject: [PATCH 056/184] Enable building on FreeBSD --- Makefile | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9cdb8d2db..7c5cab8d3 100644 --- a/Makefile +++ b/Makefile @@ -31,6 +31,7 @@ SANITIZER = # SANITIZER = cfi +OS := $(shell uname -s) PREFIX ?= /usr/local INSTALL_SUDO := @@ -216,6 +217,9 @@ endif ifeq ($(ENABLE_READLINE),1) CXXFLAGS += -DYOSYS_ENABLE_READLINE +ifeq ($(OS), FreeBSD) +CXXFLAGS += -I/usr/local/include +endif LDLIBS += -lreadline ifeq ($(LINK_CURSES),1) LDLIBS += -lcurses @@ -237,21 +241,33 @@ endif ifeq ($(ENABLE_PLUGINS),1) CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags libffi) -DYOSYS_ENABLE_PLUGINS -LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs libffi || echo -lffi) -ldl +LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs libffi || echo -lffi) +ifneq ($(OS), FreeBSD) +LDLIBS += -ldl +endif endif ifeq ($(ENABLE_TCL),1) TCL_VERSION ?= tcl$(shell bash -c "tclsh <(echo 'puts [info tclversion]')") +ifeq ($(OS), FreeBSD) +TCL_INCLUDE ?= /usr/local/include/$(TCL_VERSION) +else TCL_INCLUDE ?= /usr/include/$(TCL_VERSION) +endif ifeq ($(CONFIG),mxe) CXXFLAGS += -DYOSYS_ENABLE_TCL LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 else CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL +ifeq ($(OS), FreeBSD) +# FreeBSD uses tcl8.6, but lib is named "libtcl86" +LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs tcl || echo -l$(TCL_VERSION) | tr -d '.') +else LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs tcl || echo -l$(TCL_VERSION)) endif endif +endif ifeq ($(ENABLE_GPROF),1) CXXFLAGS += -pg From 0295213bec84683a72814bd53179fa57ee48fbbe Mon Sep 17 00:00:00 2001 From: Johnny Sorocil Date: Sun, 6 May 2018 15:26:23 +0200 Subject: [PATCH 057/184] autotest.sh: Change from /bin/bash to /usr/bin/env bash This enables running tests on Unix systems which are not shipped with bash installed in /bin/bash (eg *BSDs and Solaris). --- tests/tools/autotest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index d0b0a89d7..31a6ae8ab 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash libs="" genvcd=false From 5b9f73cd91a899a209b79e72a1030864b2f53317 Mon Sep 17 00:00:00 2001 From: Johnny Sorocil Date: Sun, 6 May 2018 18:22:18 +0200 Subject: [PATCH 058/184] update README --- README.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/README.md b/README.md index 2a7a3b6ee..d5184bd7d 100644 --- a/README.md +++ b/README.md @@ -61,6 +61,14 @@ Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies $ sudo port install bison flex readline gawk libffi \ git mercurial graphviz pkgconfig python36 +On FreeBSD use the following command to install all prerequisites: + + # pkg install bison flex readline gawk libffi\ + git mercurial graphviz pkgconfig python3 python36 tcl-wrapper + +On FreeBSD system use gmake instead of make. To run tests use: + % MAKE=gmake CC=cc gmake test + There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well as a source distribution for Visual Studio. Visit the Yosys download page for more information: http://www.clifford.at/yosys/download.html From 11406a80821cef25774921338a84849a96e61631 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 12 May 2018 13:59:13 +0200 Subject: [PATCH 059/184] Add "hierarchy -simcheck" Signed-off-by: Clifford Wolf --- passes/hierarchy/hierarchy.cc | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index ba960faf4..18dfa7184 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -138,7 +138,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, } } -bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, std::vector &libdirs) +bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, bool flag_simcheck, std::vector &libdirs) { bool did_something = false; std::map> array_cells; @@ -190,7 +190,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check } } - if (flag_check && cell->type[0] != '$') + if ((flag_check || flag_simcheck) && cell->type[0] != '$') log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n", cell->type.c_str(), module->name.c_str(), cell->name.c_str()); continue; @@ -200,7 +200,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str()); did_something = true; } else - if (flag_check) + if (flag_check || flag_simcheck) { RTLIL::Module *mod = design->module(cell->type); for (auto &conn : cell->connections()) @@ -218,10 +218,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check log_id(cell->type), log_id(module), log_id(cell), log_id(param.first)); } - if (cell->parameters.size() == 0) + if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) { + if (flag_simcheck) + log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox module.\n", + cell->type.c_str(), module->name.c_str(), cell->name.c_str()); continue; + } - if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) + if (cell->parameters.size() == 0) continue; RTLIL::Module *mod = design->modules_[cell->type]; @@ -354,6 +358,10 @@ struct HierarchyPass : public Pass { log(" also check the design hierarchy. this generates an error when\n"); log(" an unknown module is used as cell type.\n"); log("\n"); + log(" -simcheck\n"); + log(" like -check, but also thow an error if blackbox modules are\n"); + log(" instantiated, and throw an error if the design has no top module\n"); + log("\n"); log(" -purge_lib\n"); log(" by default the hierarchy command will not remove library (blackbox)\n"); log(" modules. use this option to also remove unused blackbox modules.\n"); @@ -410,6 +418,7 @@ struct HierarchyPass : public Pass { log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); bool flag_check = false; + bool flag_simcheck = false; bool purge_lib = false; RTLIL::Module *top_mod = NULL; std::vector libdirs; @@ -425,7 +434,7 @@ struct HierarchyPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-generate" && !flag_check && !top_mod) { + if (args[argidx] == "-generate" && !flag_check && !flag_simcheck && !top_mod) { generate_mode = true; log("Entering generate mode.\n"); while (++argidx < args.size()) { @@ -468,6 +477,10 @@ struct HierarchyPass : public Pass { flag_check = true; continue; } + if (args[argidx] == "-simcheck") { + flag_simcheck = true; + continue; + } if (args[argidx] == "-purge_lib") { purge_lib = true; continue; @@ -534,6 +547,9 @@ struct HierarchyPass : public Pass { log("Automatically selected %s as design top module.\n", log_id(top_mod)); } + if (flag_simcheck && top_mod == nullptr) + log_error("Design has no top module.\n"); + bool did_something = true; while (did_something) { @@ -549,7 +565,7 @@ struct HierarchyPass : public Pass { } for (auto module : used_modules) { - if (expand_module(design, module, flag_check, libdirs)) + if (expand_module(design, module, flag_check, flag_simcheck, libdirs)) did_something = true; } } From 587056447e20a3240d72392232b370790426613c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 12 May 2018 15:18:27 +0200 Subject: [PATCH 060/184] Add optimization of tristate buffer with constant control input Signed-off-by: Clifford Wolf --- passes/opt/opt_expr.cc | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 45331aa0b..a54a5c6b8 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -718,6 +718,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } + if (cell->type == "$_TBUF_" || cell->type == "$tribuf") { + RTLIL::SigSpec input = cell->getPort(cell->type == "$_TBUF_" ? "\\E" : "\\EN"); + RTLIL::SigSpec a = cell->getPort("\\A"); + assign_map.apply(input); + assign_map.apply(a); + if (input == State::S1) + ACTION_DO("\\Y", cell->getPort("\\A")); + if (input == State::S0 && !a.is_fully_undef()) { + cover("opt.opt_expr.action_" S__LINE__); + log("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n", + cell->type.c_str(), cell->name.c_str(), module->name.c_str()); + cell->setPort("\\A", SigSpec(State::Sx, GetSize(a))); + did_something = true; + goto next_cell; + } + } + if (cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex") { RTLIL::SigSpec a = cell->getPort("\\A"); From 7d076f071e83f1533623f2508794e28c79e02294 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Sat, 12 May 2018 19:53:24 +0100 Subject: [PATCH 061/184] Also interpret '&' in liberty functions --- frontends/liberty/liberty.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 877b1883e..c9b6a54b2 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -188,7 +188,7 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr) } token_t next_token(0); - if (*expr == '(' || *expr == ')' || *expr == '\'' || *expr == '!' || *expr == '^' || *expr == '*' || *expr == '+' || *expr == '|') + if (*expr == '(' || *expr == ')' || *expr == '\'' || *expr == '!' || *expr == '^' || *expr == '*' || *expr == '+' || *expr == '|' || *expr == '&') next_token = token_t(*(expr++)); else next_token = token_t(0, parse_func_identifier(module, expr)); From 1167538d265b634d6d4d825e9d92d2211f7beee9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 13 May 2018 13:06:36 +0200 Subject: [PATCH 062/184] Revert "Add "#ifdef __FreeBSD__"" This reverts commit e3575a86c525f2511902e7022893c3923ba8093e. --- kernel/driver.cc | 24 +++--------------------- kernel/log.cc | 6 +++--- kernel/log.h | 2 +- kernel/yosys.cc | 27 +-------------------------- passes/cmds/cover.cc | 2 +- 5 files changed, 9 insertions(+), 52 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index bec872c24..7a1dce497 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -34,17 +34,12 @@ #include #include -#if defined (__linux__) || defined(__FreeBSD__) +#ifdef __linux__ # include # include # include #endif -#ifdef __FreeBSD__ -# include -# include -#endif - #if !defined(_WIN32) || defined(__MINGW32__) # include #else @@ -515,7 +510,7 @@ int main(int argc, char **argv) #else std::string meminfo; std::string stats_divider = ", "; -# if defined(__linux__) +# ifdef __linux__ std::ifstream statm; statm.open(stringf("/proc/%lld/statm", (long long)getpid())); if (statm.is_open()) { @@ -526,19 +521,6 @@ int main(int argc, char **argv) sz_resident * (getpagesize() / 1024.0 / 1024.0)); stats_divider = "\n"; } -# elif defined(__FreeBSD__) - pid_t pid = getpid(); - int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PID, (int)pid}; - struct kinfo_proc kip; - size_t kip_len = sizeof(kip); - if (sysctl(mib, 4, &kip, &kip_len, NULL, 0) == 0) { - vm_size_t sz_total = kip.ki_size; - segsz_t sz_resident = kip.ki_rssize; - meminfo = stringf(", MEM: %.2f MB total, %.2f MB resident", - (int)sz_total / 1024.0 / 1024.0, - (int)sz_resident * (getpagesize() / 1024.0 / 1024.0)); - stats_divider = "\n"; - } # endif struct rusage ru_buffer; @@ -582,7 +564,7 @@ int main(int argc, char **argv) } } -#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) +#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE")) { string filename; diff --git a/kernel/log.cc b/kernel/log.cc index 6d562b9e6..ff171f3e6 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -25,7 +25,7 @@ # include #endif -#if defined(__linux__) || defined(__FreeBSD__) +#ifdef __linux__ # include #endif @@ -392,7 +392,7 @@ void log_pop() log_flush(); } -#if (defined(__linux__) || defined(__FreeBSD__)) && defined(YOSYS_ENABLE_PLUGINS) +#if defined(__linux__) && defined(YOSYS_ENABLE_PLUGINS) void log_backtrace(const char *prefix, int levels) { if (levels <= 0) return; @@ -587,7 +587,7 @@ void log_wire(RTLIL::Wire *wire, std::string indent) // --------------------------------------------------- // This is the magic behind the code coverage counters // --------------------------------------------------- -#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) +#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) dict> extra_coverage_data; diff --git a/kernel/log.h b/kernel/log.h index a2aacfd4d..457229c87 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -114,7 +114,7 @@ static inline void log_assert_worker(bool cond, const char *expr, const char *fi // This is the magic behind the code coverage counters // --------------------------------------------------- -#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) +#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) #define cover(_id) do { \ static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \ diff --git a/kernel/yosys.cc b/kernel/yosys.cc index aa5901271..49d644548 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -46,15 +46,10 @@ # include # include # include -# include # include # include #endif -#ifdef __FreeBSD__ -# include -#endif - #include #include @@ -77,7 +72,7 @@ std::vector memhasher_store; void memhasher_on() { -#if defined(__linux__) || defined(__FreeBSD__) +#ifdef __linux__ memhasher_rng += time(NULL) << 16 ^ getpid(); #endif memhasher_store.resize(0x10000); @@ -672,26 +667,6 @@ std::string proc_self_dirname() buflen--; return std::string(path, buflen); } -#elif defined(__FreeBSD__) -std::string proc_self_dirname() -{ - int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PATHNAME, -1}; - size_t buflen; - char *buffer; - std::string path; - if (sysctl(mib, 4, NULL, &buflen, NULL, 0) != 0) - log_error("sysctl failed: %s\n", strerror(errno)); - buffer = (char*)malloc(buflen); - if (buffer == NULL) - log_error("malloc failed: %s\n", strerror(errno)); - if (sysctl(mib, 4, buffer, &buflen, NULL, 0) != 0) - log_error("sysctl failed: %s\n", strerror(errno)); - while (buflen > 0 && buffer[buflen-1] != '/') - buflen--; - path.assign(buffer, buflen); - free(buffer); - return path; -} #elif defined(__APPLE__) std::string proc_self_dirname() { diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index ef4f3f7d0..1475475c3 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -128,7 +128,7 @@ struct CoverPass : public Pass { log("\n"); } -#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) +#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) for (auto &it : get_coverage_data()) { if (!patterns.empty()) { for (auto &p : patterns) From c1ecb1b2f1427e5d8616c9177c6962ebf1449a47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20Kr=C3=A4mer?= Date: Sat, 5 May 2018 13:02:44 +0200 Subject: [PATCH 063/184] Add "#ifdef __FreeBSD__" (Re-commit e3575a8 with corrected author field) --- kernel/driver.cc | 24 +++++++++++++++++++++--- kernel/log.cc | 6 +++--- kernel/log.h | 2 +- kernel/yosys.cc | 27 ++++++++++++++++++++++++++- passes/cmds/cover.cc | 2 +- 5 files changed, 52 insertions(+), 9 deletions(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index 7a1dce497..bec872c24 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -34,12 +34,17 @@ #include #include -#ifdef __linux__ +#if defined (__linux__) || defined(__FreeBSD__) # include # include # include #endif +#ifdef __FreeBSD__ +# include +# include +#endif + #if !defined(_WIN32) || defined(__MINGW32__) # include #else @@ -510,7 +515,7 @@ int main(int argc, char **argv) #else std::string meminfo; std::string stats_divider = ", "; -# ifdef __linux__ +# if defined(__linux__) std::ifstream statm; statm.open(stringf("/proc/%lld/statm", (long long)getpid())); if (statm.is_open()) { @@ -521,6 +526,19 @@ int main(int argc, char **argv) sz_resident * (getpagesize() / 1024.0 / 1024.0)); stats_divider = "\n"; } +# elif defined(__FreeBSD__) + pid_t pid = getpid(); + int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PID, (int)pid}; + struct kinfo_proc kip; + size_t kip_len = sizeof(kip); + if (sysctl(mib, 4, &kip, &kip_len, NULL, 0) == 0) { + vm_size_t sz_total = kip.ki_size; + segsz_t sz_resident = kip.ki_rssize; + meminfo = stringf(", MEM: %.2f MB total, %.2f MB resident", + (int)sz_total / 1024.0 / 1024.0, + (int)sz_resident * (getpagesize() / 1024.0 / 1024.0)); + stats_divider = "\n"; + } # endif struct rusage ru_buffer; @@ -564,7 +582,7 @@ int main(int argc, char **argv) } } -#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) +#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) if (getenv("YOSYS_COVER_DIR") || getenv("YOSYS_COVER_FILE")) { string filename; diff --git a/kernel/log.cc b/kernel/log.cc index ff171f3e6..6d562b9e6 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -25,7 +25,7 @@ # include #endif -#ifdef __linux__ +#if defined(__linux__) || defined(__FreeBSD__) # include #endif @@ -392,7 +392,7 @@ void log_pop() log_flush(); } -#if defined(__linux__) && defined(YOSYS_ENABLE_PLUGINS) +#if (defined(__linux__) || defined(__FreeBSD__)) && defined(YOSYS_ENABLE_PLUGINS) void log_backtrace(const char *prefix, int levels) { if (levels <= 0) return; @@ -587,7 +587,7 @@ void log_wire(RTLIL::Wire *wire, std::string indent) // --------------------------------------------------- // This is the magic behind the code coverage counters // --------------------------------------------------- -#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) +#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) dict> extra_coverage_data; diff --git a/kernel/log.h b/kernel/log.h index 457229c87..a2aacfd4d 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -114,7 +114,7 @@ static inline void log_assert_worker(bool cond, const char *expr, const char *fi // This is the magic behind the code coverage counters // --------------------------------------------------- -#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) +#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) #define cover(_id) do { \ static CoverData __d __attribute__((section("yosys_cover_list"), aligned(1), used)) = { __FILE__, __FUNCTION__, _id, __LINE__, 0 }; \ diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 49d644548..aa5901271 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -46,10 +46,15 @@ # include # include # include +# include # include # include #endif +#ifdef __FreeBSD__ +# include +#endif + #include #include @@ -72,7 +77,7 @@ std::vector memhasher_store; void memhasher_on() { -#ifdef __linux__ +#if defined(__linux__) || defined(__FreeBSD__) memhasher_rng += time(NULL) << 16 ^ getpid(); #endif memhasher_store.resize(0x10000); @@ -667,6 +672,26 @@ std::string proc_self_dirname() buflen--; return std::string(path, buflen); } +#elif defined(__FreeBSD__) +std::string proc_self_dirname() +{ + int mib[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PATHNAME, -1}; + size_t buflen; + char *buffer; + std::string path; + if (sysctl(mib, 4, NULL, &buflen, NULL, 0) != 0) + log_error("sysctl failed: %s\n", strerror(errno)); + buffer = (char*)malloc(buflen); + if (buffer == NULL) + log_error("malloc failed: %s\n", strerror(errno)); + if (sysctl(mib, 4, buffer, &buflen, NULL, 0) != 0) + log_error("sysctl failed: %s\n", strerror(errno)); + while (buflen > 0 && buffer[buflen-1] != '/') + buflen--; + path.assign(buffer, buflen); + free(buffer); + return path; +} #elif defined(__APPLE__) std::string proc_self_dirname() { diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 1475475c3..ef4f3f7d0 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -128,7 +128,7 @@ struct CoverPass : public Pass { log("\n"); } -#if defined(YOSYS_ENABLE_COVER) && defined(__linux__) +#if defined(YOSYS_ENABLE_COVER) && (defined(__linux__) || defined(__FreeBSD__)) for (auto &it : get_coverage_data()) { if (!patterns.empty()) { for (auto &p : patterns) From ae33026799e0f6e05d00557e8f98f5805e3d6f13 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 13 May 2018 13:29:18 +0200 Subject: [PATCH 064/184] Use $(OS) in makefile to check for Darwin Signed-off-by: Clifford Wolf --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 7c5cab8d3..1caa0038b 100644 --- a/Makefile +++ b/Makefile @@ -67,7 +67,7 @@ SED ?= sed BISON ?= bison STRIP ?= strip -ifeq (Darwin,$(findstring Darwin,$(shell uname))) +ifeq ($(OS), Darwin) PLUGIN_LDFLAGS += -undefined dynamic_lookup # homebrew search paths From 0fad1570b5ab07aabf212242039921c63d1db32a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 13 May 2018 16:36:12 +0200 Subject: [PATCH 065/184] Some cleanups in setundef.cc Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 389c3790e..c11ddbdc1 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -40,6 +40,9 @@ struct SetundefWorker if (next_bit_mode == 1) return RTLIL::State::S1; + if (next_bit_mode == 2) + log_abort(); + if (next_bit_mode == 4) return RTLIL::State::Sx; @@ -117,21 +120,25 @@ struct SetundefPass : public Pass { if (args[argidx] == "-zero") { got_value = true; worker.next_bit_mode = 0; + worker.next_bit_state = 0; continue; } if (args[argidx] == "-one") { got_value = true; worker.next_bit_mode = 1; + worker.next_bit_state = 0; continue; } if (args[argidx] == "-anyseq") { got_value = true; worker.next_bit_mode = 2; + worker.next_bit_state = 0; continue; } if (args[argidx] == "-undef") { got_value = true; worker.next_bit_mode = 4; + worker.next_bit_state = 0; continue; } if (args[argidx] == "-init") { From 9286acb6870876f27771c039704ded7d9ffef3a9 Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Sun, 13 May 2018 16:53:35 -0400 Subject: [PATCH 066/184] Add option -expose to setundef pass Option -expose converts undriven wires to inputs. Example usage: setundef -undriven -expose [selection] --- passes/cmds/setundef.cc | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index c11ddbdc1..172b1c3f8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -81,6 +81,9 @@ struct SetundefPass : public Pass { log(" -undriven\n"); log(" also set undriven nets to constant values\n"); log("\n"); + log(" -expose\n"); + log(" also expose undriven nets as inputs\n"); + log("\n"); log(" -zero\n"); log(" replace with bits cleared (0)\n"); log("\n"); @@ -105,6 +108,7 @@ struct SetundefPass : public Pass { { bool got_value = false; bool undriven_mode = false; + bool expose_mode = false; bool init_mode = false; SetundefWorker worker; @@ -117,6 +121,11 @@ struct SetundefPass : public Pass { undriven_mode = true; continue; } + if (args[argidx] == "-expose") { + got_value = true; + expose_mode = true; + continue; + } if (args[argidx] == "-zero") { got_value = true; worker.next_bit_mode = 0; @@ -157,6 +166,8 @@ struct SetundefPass : public Pass { } extra_args(args, argidx, design); + if (expose_mode && !undriven_mode) + log_cmd_error("Option -expose must be used with option -undriven.\n"); if (!got_value) log_cmd_error("One of the options -zero, -one, -anyseq, or -random must be specified.\n"); @@ -184,12 +195,21 @@ struct SetundefPass : public Pass { undriven_signals.del(sigmap(conn.second)); RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks()) { - RTLIL::SigSpec bits; - for (int i = 0; i < c.width; i++) - bits.append(worker.next_bit()); - module->connect(RTLIL::SigSig(c, bits)); - } + if (expose_mode) { + for (auto &c : sig.chunks()) { + c.wire->port_input = true; + log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(c.wire->name)); + } + module->fixup_ports(); + } + else { + for (auto &c : sig.chunks()) { + RTLIL::SigSpec bits; + for (int i = 0; i < c.width; i++) + bits.append(worker.next_bit()); + module->connect(RTLIL::SigSig(c, bits)); + } + } } if (init_mode) From b4a303a1b7a9986881efa1040bf54c5f583d87a0 Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Sun, 13 May 2018 20:13:54 -0400 Subject: [PATCH 067/184] Corrections to option -expose in setundef pass --- passes/cmds/setundef.cc | 163 +++++++++++++++++++++++++++++++++++----- 1 file changed, 144 insertions(+), 19 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 172b1c3f8..0825cf83e 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -26,6 +26,70 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global) +{ + RTLIL::Wire *wire = NULL; + name = RTLIL::escape_id(name); + + if (module->count_id(name) != 0) + { + if (module->wires_.count(name) > 0) + wire = module->wires_.at(name); + + if (wire != NULL && wire->width != width) + wire = NULL; + + if (wire != NULL && wire->port_input != flag_input) + wire = NULL; + + if (wire != NULL && wire->port_output != flag_output) + wire = NULL; + + if (wire == NULL) { + return wire; + log_cmd_error("Found incompatible object %s with same name in module %s!\n", name.c_str(), module->name.c_str()); + } + + log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str()); + } + else + { + wire = module->addWire(name, width); + wire->port_input = flag_input; + wire->port_output = flag_output; + + if (flag_input || flag_output) { + wire->port_id = module->wires_.size(); + module->fixup_ports(); + } + + log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); + } + + if (!flag_global) + return wire; + + for (auto &it : module->cells_) + { + if (design->modules_.count(it.second->type) == 0) + continue; + + RTLIL::Module *mod = design->modules_.at(it.second->type); + if (!design->selected_whole_module(mod->name)) + continue; + if (mod->get_bool_attribute("\\blackbox")) + continue; + if (it.second->hasPort(name)) + continue; + + it.second->setPort(name, wire); + log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); + } + + return wire; +} + + struct SetundefWorker { int next_bit_mode; @@ -178,31 +242,92 @@ struct SetundefPass : public Pass { if (!module->processes.empty()) log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n"); - SigMap sigmap(module); - SigPool undriven_signals; - - for (auto &it : module->wires_) - undriven_signals.add(sigmap(it.second)); - - for (auto &it : module->wires_) - if (it.second->port_input) - undriven_signals.del(sigmap(it.second)); - - CellTypes ct(design); - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) - undriven_signals.del(sigmap(conn.second)); - - RTLIL::SigSpec sig = undriven_signals.export_all(); if (expose_mode) { + SigMap sigmap(module); + dict wire_drivers; + pool used_wires; + SigPool undriven_signals; + + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) { + SigSpec sig = sigmap(conn.second); + if (cell->input(conn.first)) + for (auto bit : sig) + if (bit.wire) { + used_wires.insert(bit); + } + if (cell->output(conn.first)) + for (int i = 0; i < GetSize(sig); i++) { + if (sig[i].wire) + wire_drivers[sig[i]] = true; + } + } + + for (auto wire : module->wires()) { + if (wire->port_input) { + SigSpec sig = sigmap(wire); + for (int i = 0; i < GetSize(sig); i++) + wire_drivers[sig[i]] = true; + } + if (wire->port_output) + for (auto bit : sigmap(wire)) + if (bit.wire) used_wires.insert(bit); + } + + pool undriven_wires; + for (auto bit : used_wires) { + if (!wire_drivers.count(bit)) { + undriven_wires.insert(bit.wire); + } + } + + for (auto &it : undriven_wires) + undriven_signals.add(sigmap(it)); + + for (auto &it : undriven_wires) + if (it->port_input) + undriven_signals.del(sigmap(it)); + + CellTypes ct(design); + for (auto &it : module->cells_) + for (auto &conn : it.second->connections()) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); + + RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { - c.wire->port_input = true; - log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(c.wire->name)); + RTLIL::Wire * wire; + if (c.wire->width == c.width) { + wire = c.wire; + wire->port_input = true; + } + else { + string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; + wire = add_wire(design, module, name, c.width, true, false, false); + module->connect(RTLIL::SigSig(c.wire, wire)); + } + log("Exposing undriven wire %s as input.\n", wire->name.c_str()); } module->fixup_ports(); } else { + SigMap sigmap(module); + SigPool undriven_signals; + + for (auto &it : module->wires_) + undriven_signals.add(sigmap(it.second)); + + for (auto &it : module->wires_) + if (it.second->port_input) + undriven_signals.del(sigmap(it.second)); + + CellTypes ct(design); + for (auto &it : module->cells_) + for (auto &conn : it.second->connections()) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); + + RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) From 8b9a8c7f9115e691dc832b3be3d82b55be507e99 Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Mon, 14 May 2018 18:58:49 -0400 Subject: [PATCH 068/184] Minor correction Minor typo error correction in -expose with setundef --- passes/cmds/setundef.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 0825cf83e..9b0c30cae 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -89,7 +89,6 @@ static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std: return wire; } - struct SetundefWorker { int next_bit_mode; @@ -304,7 +303,7 @@ struct SetundefPass : public Pass { else { string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; wire = add_wire(design, module, name, c.width, true, false, false); - module->connect(RTLIL::SigSig(c.wire, wire)); + module->connect(RTLIL::SigSig(c, wire)); } log("Exposing undriven wire %s as input.\n", wire->name.c_str()); } From edd297fb1cb2d02a01b433327cb513399a171062 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 15 May 2018 13:13:43 +0200 Subject: [PATCH 069/184] Fix iopadmap for cases where IO pins already have buffers on them Signed-off-by: Clifford Wolf --- passes/techmap/iopadmap.cc | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 4acbf7c0d..c20081c64 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -146,10 +146,34 @@ struct IopadmapPass : public Pass { for (auto module : design->selected_modules()) { dict> skip_wires; + pool skip_wire_bits; + SigMap sigmap(module); + + for (auto cell : module->cells()) + { + if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2))) + for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2)))) + skip_wire_bits.insert(bit); + + if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2))) + for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2)))) + skip_wire_bits.insert(bit); + + if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2))) + for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2)))) + skip_wire_bits.insert(bit); + + if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3))) + for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3)))) + skip_wire_bits.insert(bit); + + if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4))) + for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4)))) + skip_wire_bits.insert(bit); + } if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty()) { - SigMap sigmap(module); dict>> tbuf_bits; for (auto cell : module->cells()) @@ -177,6 +201,9 @@ struct IopadmapPass : public Pass { if (tbuf_bits.count(mapped_wire_bit) == 0) continue; + if (skip_wire_bits.count(mapped_wire_bit)) + continue; + auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit); Cell *tbuf_cell = module->cell(tbuf_cache.first); @@ -272,6 +299,13 @@ struct IopadmapPass : public Pass { skip_bit_indices = skip_wires.at(wire->name); } + for (int i = 0; i < GetSize(wire); i++) + if (skip_wire_bits.count(sigmap(SigBit(wire, i)))) + skip_bit_indices.insert(i); + + if (GetSize(wire) == GetSize(skip_bit_indices)) + continue; + if (wire->port_input && !wire->port_output) { if (inpad_celltype.empty()) { log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name)); From fe80b39f56fb650cc67bed09f29ea42e0e5f6e52 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 15 May 2018 14:02:27 +0200 Subject: [PATCH 070/184] Fix iopadmap for loops between tristate IO buffers Signed-off-by: Clifford Wolf --- passes/techmap/iopadmap.cc | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index c20081c64..690ba87ed 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -175,6 +175,8 @@ struct IopadmapPass : public Pass { if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty()) { dict>> tbuf_bits; + pool> norewrites; + SigMap rewrites; for (auto cell : module->cells()) if (cell->type == "$_TBUF_") { @@ -246,6 +248,9 @@ struct IopadmapPass : public Pass { module->remove(tbuf_cell); skip_wires[wire->name].insert(i); + + norewrites.insert(make_pair(cell->name, RTLIL::escape_id(tinoutpad_portname4))); + rewrites.add(sigmap(wire_bit), owire); continue; } @@ -283,6 +288,22 @@ struct IopadmapPass : public Pass { } } } + + if (GetSize(norewrites)) + { + for (auto cell : module->cells()) + for (auto port : cell->connections()) + { + if (norewrites.count(make_pair(cell->name, port.first))) + continue; + + SigSpec orig_sig = sigmap(port.second); + SigSpec new_sig = rewrites(orig_sig); + + if (orig_sig != new_sig) + cell->setPort(port.first, new_sig); + } + } } for (auto wire : module->selected_wires()) From 4b6c0e331d0ef4188f8fa2443f8f7999231af052 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 15 May 2018 14:19:05 +0200 Subject: [PATCH 071/184] Remove mercurial from build instructions Signed-off-by: Clifford Wolf --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index d5184bd7d..704948e2d 100644 --- a/README.md +++ b/README.md @@ -52,19 +52,19 @@ For example on Ubuntu Linux 16.04 LTS the following commands will install all prerequisites for building yosys: $ sudo apt-get install build-essential clang bison flex \ - libreadline-dev gawk tcl-dev libffi-dev git mercurial \ + libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies: $ brew tap Homebrew/bundle && brew bundle $ sudo port install bison flex readline gawk libffi \ - git mercurial graphviz pkgconfig python36 + git graphviz pkgconfig python36 On FreeBSD use the following command to install all prerequisites: # pkg install bison flex readline gawk libffi\ - git mercurial graphviz pkgconfig python3 python36 tcl-wrapper + git graphviz pkgconfig python3 python36 tcl-wrapper On FreeBSD system use gmake instead of make. To run tests use: % MAKE=gmake CC=cc gmake test From 6e63df6dd08fe424f46039d26f9f238ac1cb4494 Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Tue, 15 May 2018 13:06:23 -0400 Subject: [PATCH 072/184] Correction to -expose with setundef --- passes/cmds/setundef.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 9b0c30cae..c67953976 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -308,6 +308,7 @@ struct SetundefPass : public Pass { log("Exposing undriven wire %s as input.\n", wire->name.c_str()); } module->fixup_ports(); + continue; } else { SigMap sigmap(module); From a7281930c5877b34e072d90d5ca013f8fda7e2cc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 15 May 2018 19:27:00 +0200 Subject: [PATCH 073/184] Fix handling of anyconst/anyseq attrs in VHDL code via Verific Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ee09c7523..624c04be9 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -871,22 +871,22 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se const char *allconst_attr = net->GetAttValue("allconst"); const char *allseq_attr = net->GetAttValue("allseq"); - if (rand_const_attr != nullptr && !strcmp(rand_const_attr, "1")) + if (rand_const_attr != nullptr && (!strcmp(rand_const_attr, "1") || !strcmp(rand_const_attr, "'1'"))) anyconst_nets.insert(net); - else if (rand_attr != nullptr && !strcmp(rand_attr, "1")) + else if (rand_attr != nullptr && (!strcmp(rand_attr, "1") || !strcmp(rand_attr, "'1'"))) anyseq_nets.insert(net); - else if (anyconst_attr != nullptr && !strcmp(anyconst_attr, "1")) + else if (anyconst_attr != nullptr && (!strcmp(anyconst_attr, "1") || !strcmp(anyconst_attr, "'1'"))) anyconst_nets.insert(net); - else if (anyseq_attr != nullptr && !strcmp(anyseq_attr, "1")) + else if (anyseq_attr != nullptr && (!strcmp(anyseq_attr, "1") || !strcmp(anyseq_attr, "'1'"))) anyseq_nets.insert(net); - else if (allconst_attr != nullptr && !strcmp(allconst_attr, "1")) + else if (allconst_attr != nullptr && (!strcmp(allconst_attr, "1") || !strcmp(allconst_attr, "'1'"))) allconst_nets.insert(net); - else if (allseq_attr != nullptr && !strcmp(allseq_attr, "1")) + else if (allseq_attr != nullptr && (!strcmp(allseq_attr, "1") || !strcmp(allseq_attr, "'1'"))) allseq_nets.insert(net); if (net_map.count(net)) { From 872d8d49e98fc5a4090ce20d902afbd0090c8c84 Mon Sep 17 00:00:00 2001 From: Jim Paris Date: Thu, 17 May 2018 00:06:49 -0400 Subject: [PATCH 074/184] Skip spaces around macro arguments --- frontends/verilog/preproc.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index c43ff4e3a..00124cb42 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -244,6 +244,7 @@ static bool try_expand_macro(std::set &defines_with_args, args.push_back(std::string()); while (1) { + skip_spaces(); tok = next_token(true); if (tok == ")" || tok == "}" || tok == "]") level--; From 4a229e5b953c15ecb31945258e0ca2f7bffe8a3e Mon Sep 17 00:00:00 2001 From: Jim Paris Date: Thu, 17 May 2018 00:09:56 -0400 Subject: [PATCH 075/184] Support SystemVerilog `` extension for macros --- frontends/verilog/preproc.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 00124cb42..dea22ee8a 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -183,8 +183,9 @@ static std::string next_token(bool pass_newline = false) const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789"; if (ch == '`' || strchr(ok, ch) != NULL) { + char first = ch; ch = next_char(); - if (ch == '"') { + if (first == '`' && (ch == '"' || ch == '`')) { token += ch; } else do { if (strchr(ok, ch) == NULL) { @@ -265,6 +266,9 @@ static bool try_expand_macro(std::set &defines_with_args, } insert_input(defines_map[name]); return true; + } else if (tok == "``") { + // Swallow `` in macro expansion + return true; } else return false; } From faac2c559565a25e58ce95a7ea873df0c30375dc Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Thu, 17 May 2018 13:54:40 +0200 Subject: [PATCH 076/184] Avoid mixing module port declaration styles in ice40 cells_sim.v The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax. --- techlibs/ice40/cells_sim.v | 66 +++++++++++++------------------------- 1 file changed, 23 insertions(+), 43 deletions(-) diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 814895e70..45a02111f 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1,6 +1,6 @@ -`define SB_DFF_REG reg Q = 0; -// `define SB_DFF_REG reg Q; +`define SB_DFF_REG reg Q = 0 +// `define SB_DFF_REG reg Q // SiliconBlue IO Cells @@ -132,21 +132,18 @@ endmodule // Positive Edge SiliconBlue FF Cells -module SB_DFF (output Q, input C, D); - `SB_DFF_REG +module SB_DFF (output `SB_DFF_REG, input C, D); always @(posedge C) Q <= D; endmodule -module SB_DFFE (output Q, input C, E, D); - `SB_DFF_REG +module SB_DFFE (output `SB_DFF_REG, input C, E, D); always @(posedge C) if (E) Q <= D; endmodule -module SB_DFFSR (output Q, input C, R, D); - `SB_DFF_REG +module SB_DFFSR (output `SB_DFF_REG, input C, R, D); always @(posedge C) if (R) Q <= 0; @@ -154,8 +151,7 @@ module SB_DFFSR (output Q, input C, R, D); Q <= D; endmodule -module SB_DFFR (output Q, input C, R, D); - `SB_DFF_REG +module SB_DFFR (output `SB_DFF_REG, input C, R, D); always @(posedge C, posedge R) if (R) Q <= 0; @@ -163,8 +159,7 @@ module SB_DFFR (output Q, input C, R, D); Q <= D; endmodule -module SB_DFFSS (output Q, input C, S, D); - `SB_DFF_REG +module SB_DFFSS (output `SB_DFF_REG, input C, S, D); always @(posedge C) if (S) Q <= 1; @@ -172,8 +167,7 @@ module SB_DFFSS (output Q, input C, S, D); Q <= D; endmodule -module SB_DFFS (output Q, input C, S, D); - `SB_DFF_REG +module SB_DFFS (output `SB_DFF_REG, input C, S, D); always @(posedge C, posedge S) if (S) Q <= 1; @@ -181,8 +175,7 @@ module SB_DFFS (output Q, input C, S, D); Q <= D; endmodule -module SB_DFFESR (output Q, input C, E, R, D); - `SB_DFF_REG +module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D); always @(posedge C) if (E) begin if (R) @@ -192,8 +185,7 @@ module SB_DFFESR (output Q, input C, E, R, D); end endmodule -module SB_DFFER (output Q, input C, E, R, D); - `SB_DFF_REG +module SB_DFFER (output `SB_DFF_REG, input C, E, R, D); always @(posedge C, posedge R) if (R) Q <= 0; @@ -201,8 +193,7 @@ module SB_DFFER (output Q, input C, E, R, D); Q <= D; endmodule -module SB_DFFESS (output Q, input C, E, S, D); - `SB_DFF_REG +module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D); always @(posedge C) if (E) begin if (S) @@ -212,8 +203,7 @@ module SB_DFFESS (output Q, input C, E, S, D); end endmodule -module SB_DFFES (output Q, input C, E, S, D); - `SB_DFF_REG +module SB_DFFES (output `SB_DFF_REG, input C, E, S, D); always @(posedge C, posedge S) if (S) Q <= 1; @@ -223,21 +213,18 @@ endmodule // Negative Edge SiliconBlue FF Cells -module SB_DFFN (output Q, input C, D); - `SB_DFF_REG +module SB_DFFN (output `SB_DFF_REG, input C, D); always @(negedge C) Q <= D; endmodule -module SB_DFFNE (output Q, input C, E, D); - `SB_DFF_REG +module SB_DFFNE (output `SB_DFF_REG, input C, E, D); always @(negedge C) if (E) Q <= D; endmodule -module SB_DFFNSR (output Q, input C, R, D); - `SB_DFF_REG +module SB_DFFNSR (output `SB_DFF_REG, input C, R, D); always @(negedge C) if (R) Q <= 0; @@ -245,8 +232,7 @@ module SB_DFFNSR (output Q, input C, R, D); Q <= D; endmodule -module SB_DFFNR (output Q, input C, R, D); - `SB_DFF_REG +module SB_DFFNR (output `SB_DFF_REG, input C, R, D); always @(negedge C, posedge R) if (R) Q <= 0; @@ -254,8 +240,7 @@ module SB_DFFNR (output Q, input C, R, D); Q <= D; endmodule -module SB_DFFNSS (output Q, input C, S, D); - `SB_DFF_REG +module SB_DFFNSS (output `SB_DFF_REG, input C, S, D); always @(negedge C) if (S) Q <= 1; @@ -263,8 +248,7 @@ module SB_DFFNSS (output Q, input C, S, D); Q <= D; endmodule -module SB_DFFNS (output Q, input C, S, D); - `SB_DFF_REG +module SB_DFFNS (output `SB_DFF_REG, input C, S, D); always @(negedge C, posedge S) if (S) Q <= 1; @@ -272,8 +256,7 @@ module SB_DFFNS (output Q, input C, S, D); Q <= D; endmodule -module SB_DFFNESR (output Q, input C, E, R, D); - `SB_DFF_REG +module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D); always @(negedge C) if (E) begin if (R) @@ -283,8 +266,7 @@ module SB_DFFNESR (output Q, input C, E, R, D); end endmodule -module SB_DFFNER (output Q, input C, E, R, D); - `SB_DFF_REG +module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D); always @(negedge C, posedge R) if (R) Q <= 0; @@ -292,8 +274,7 @@ module SB_DFFNER (output Q, input C, E, R, D); Q <= D; endmodule -module SB_DFFNESS (output Q, input C, E, S, D); - `SB_DFF_REG +module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D); always @(negedge C) if (E) begin if (S) @@ -303,8 +284,7 @@ module SB_DFFNESS (output Q, input C, E, S, D); end endmodule -module SB_DFFNES (output Q, input C, E, S, D); - `SB_DFF_REG +module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D); always @(negedge C, posedge S) if (S) Q <= 1; @@ -677,7 +657,7 @@ module ICESTORM_LC ( parameter [0:0] SET_NORESET = 0; parameter [0:0] ASYNC_SR = 0; - wire COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx; + assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx; wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0]; From 1b210dbfb78469b477ad8e6da795d2c5ea3f8507 Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Fri, 18 May 2018 22:01:25 -0700 Subject: [PATCH 077/184] Makefile: Make abc always use stdint.h --- Makefile | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 1caa0038b..13caaab8b 100644 --- a/Makefile +++ b/Makefile @@ -126,6 +126,7 @@ ifeq ($(CONFIG),clang) CXX = clang LD = clang++ CXXFLAGS += -std=c++11 -Os +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" ifneq ($(SANITIZER),) $(info [Clang Sanitizer] $(SANITIZER)) @@ -148,16 +149,19 @@ else ifeq ($(CONFIG),gcc) CXX = gcc LD = gcc CXXFLAGS += -std=c++11 -Os +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" else ifeq ($(CONFIG),gcc-4.8) CXX = gcc-4.8 LD = gcc-4.8 CXXFLAGS += -std=c++11 -Os +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" else ifeq ($(CONFIG),emcc) CXX = emcc LD = emcc CXXFLAGS := -std=c++11 $(filter-out -fPIC -ggdb,$(CXXFLAGS)) +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" EMCCFLAGS := -Os -Wno-warn-absolute-paths EMCCFLAGS += --memory-init-file 0 --embed-file share -s NO_EXIT_RUNTIME=1 EMCCFLAGS += -s EXPORTED_FUNCTIONS="['_main','_run','_prompt','_errmsg']" @@ -192,8 +196,8 @@ CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDLIBS := $(filter-out -lrt,$(LDLIBS)) -ABCMKARGS += ARCHFLAGS="-DSIZEOF_VOID_P=4 -DSIZEOF_LONG=4 -DSIZEOF_INT=4 -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" -ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 CC="$(CXX)" CXX="$(CXX)" +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" +ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 EXE = .exe else ifeq ($(CONFIG),msys2) @@ -203,8 +207,8 @@ CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDLIBS := $(filter-out -lrt,$(LDLIBS)) -ABCMKARGS += ARCHFLAGS="-DSIZEOF_VOID_P=4 -DSIZEOF_LONG=4 -DSIZEOF_INT=4 -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" -ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)" +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" +ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=0 EXE = .exe else ifneq ($(CONFIG),none) From bfce3a74791e68a194e5c5908429334dfea3738b Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Tue, 14 Nov 2017 02:19:21 -0800 Subject: [PATCH 078/184] Add an option to statically link abc into yosys This is currently incomplete because the output filter no longer works. --- Makefile | 22 ++++++++++++++++++---- passes/techmap/abc.cc | 20 ++++++++++++++++++++ 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 13caaab8b..cc42f82d6 100644 --- a/Makefile +++ b/Makefile @@ -22,6 +22,7 @@ ENABLE_DEBUG := 0 ENABLE_NDEBUG := 0 LINK_CURSES := 0 LINK_TERMCAP := 0 +LINK_ABC := 0 # clang sanitizers SANITIZER = @@ -292,10 +293,15 @@ endif ifeq ($(ENABLE_ABC),1) CXXFLAGS += -DYOSYS_ENABLE_ABC +ifeq ($(LINK_ABC),1) +CXXFLAGS += -DYOSYS_LINK_ABC +LDLIBS += -lpthread +else ifeq ($(ABCEXTERNAL),) TARGETS += yosys-abc$(EXE) endif endif +endif ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib_eval @@ -415,6 +421,10 @@ include techlibs/common/Makefile.inc endif +ifeq ($(LINK_ABC),1) +OBJS += yosys-libabc.a +endif + top-all: $(TARGETS) $(EXTRA_TARGETS) @echo "" @echo " Build successful." @@ -459,7 +469,7 @@ yosys-config: misc/yosys-config.in -e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > yosys-config $(Q) chmod +x yosys-config -abc/abc-$(ABCREV)$(EXE): +abc/abc-$(ABCREV)$(EXE) abc/libabc-$(ABCREV).a: $(P) ifneq ($(ABCREV),default) $(Q) if test -d abc/.hg; then \ @@ -476,15 +486,19 @@ ifneq ($(ABCREV),default) fi endif $(Q) rm -f abc/abc-[0-9a-f]* - $(Q) cd abc && $(MAKE) $(S) $(ABCMKARGS) PROG="abc-$(ABCREV)$(EXE)" MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " + $(Q) cd abc && $(MAKE) $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc-$(ABCREV)",PROG="abc-$(ABCREV)$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc-$(ABCREV).a) ifeq ($(ABCREV),default) .PHONY: abc/abc-$(ABCREV)$(EXE) +.PHONY: abc/libabc-$(ABCREV).a endif yosys-abc$(EXE): abc/abc-$(ABCREV)$(EXE) $(P) cp abc/abc-$(ABCREV)$(EXE) yosys-abc$(EXE) +yosys-libabc.a: abc/libabc-$(ABCREV).a + $(P) cp abc/libabc-$(ABCREV).a yosys-libabc.a + ifneq ($(SEED),) SEEDOPT="-S $(SEED)" else @@ -568,7 +582,7 @@ clean: rm -rf share if test -d manual; then cd manual && sh clean.sh; fi rm -f $(OBJS) $(GENFILES) $(TARGETS) $(EXTRA_TARGETS) $(EXTRA_OBJS) - rm -f kernel/version_*.o kernel/version_*.cc abc/abc-[0-9a-f]* + rm -f kernel/version_*.o kernel/version_*.cc abc/abc-[0-9a-f]* abc/libabc-[0-9a-f]*.a rm -f libs/*/*.d frontends/*/*.d passes/*/*.d backends/*/*.d kernel/*.d techlibs/*/*.d rm -rf tests/asicworld/*.out tests/asicworld/*.log rm -rf tests/hana/*.out tests/hana/*.log @@ -581,7 +595,7 @@ clean: clean-abc: $(MAKE) -C abc DEP= clean - rm -f yosys-abc$(EXE) abc/abc-[0-9a-f]* + rm -f yosys-abc$(EXE) yosys-libabc.a abc/abc-[0-9a-f]* abc/libabc-[0-9a-f]*.a mrproper: clean git clean -xdf diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 009ba6b97..8e1484301 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -60,6 +60,10 @@ #include "frontends/blif/blifparse.h" +#ifdef YOSYS_LINK_ABC +extern "C" int Abc_RealMain(int argc, char *argv[]); +#endif + USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -943,8 +947,24 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str()); log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str()); +#ifndef YOSYS_LINK_ABC abc_output_filter filt(tempdir_name, show_tempdir); int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); +#else + // These needs to be mutable, supposedly due to getopt + char *abc_argv[5]; + string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str()); + abc_argv[0] = strdup(exe_file.c_str()); + abc_argv[1] = strdup("-s"); + abc_argv[2] = strdup("-f"); + abc_argv[3] = strdup(tmp_script_name.c_str()); + abc_argv[4] = 0; + int ret = Abc_RealMain(4, abc_argv); + free(abc_argv[0]); + free(abc_argv[1]); + free(abc_argv[2]); + free(abc_argv[3]); +#endif if (ret != 0) log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); From 93f79299a5138c966512f9ed2d140f16b1735b70 Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Fri, 18 May 2018 22:42:24 -0700 Subject: [PATCH 079/184] Add options to disable abc's usage of pthreads and readline --- Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Makefile b/Makefile index cc42f82d6..b664cafc4 100644 --- a/Makefile +++ b/Makefile @@ -23,6 +23,8 @@ ENABLE_NDEBUG := 0 LINK_CURSES := 0 LINK_TERMCAP := 0 LINK_ABC := 0 +# Needed for environments that don't have proper thread support (i.e. emscripten) +DISABLE_ABC_THREADS := 0 # clang sanitizers SANITIZER = @@ -241,9 +243,15 @@ else ifeq ($(ENABLE_EDITLINE),1) CXXFLAGS += -DYOSYS_ENABLE_EDITLINE LDLIBS += -ledit -ltinfo -lbsd +else +ABCMKARGS += "ABC_USE_NO_READLINE=1" endif endif +ifeq ($(DISABLE_ABC_THREADS),1) +ABCMKARGS += "ABC_USE_NO_PTHREADS=1" +endif + ifeq ($(ENABLE_PLUGINS),1) CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags libffi) -DYOSYS_ENABLE_PLUGINS LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --libs libffi || echo -lffi) @@ -295,7 +303,9 @@ ifeq ($(ENABLE_ABC),1) CXXFLAGS += -DYOSYS_ENABLE_ABC ifeq ($(LINK_ABC),1) CXXFLAGS += -DYOSYS_LINK_ABC +ifeq ($(DISABLE_ABC_THREADS),0) LDLIBS += -lpthread +endif else ifeq ($(ABCEXTERNAL),) TARGETS += yosys-abc$(EXE) From bd87462b47fdd8d7885269246ec1f7b685c6f86f Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Tue, 14 Nov 2017 04:08:07 -0800 Subject: [PATCH 080/184] Fix reading techlibs under emscripten --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index aa5901271..750a154e6 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -739,7 +739,7 @@ std::string proc_self_dirname() #ifdef EMSCRIPTEN std::string proc_share_dirname() { - return "/share"; + return "/share/"; } #else std::string proc_share_dirname() From 9763e4d830fa85aeb1577cab4dec9f4becc28f03 Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Tue, 14 Nov 2017 04:08:36 -0800 Subject: [PATCH 081/184] Fix infinite loop in abc command under emscripten --- passes/techmap/abc.cc | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 8e1484301..18868c6d7 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -550,11 +550,13 @@ std::string replace_tempdir(std::string text, std::string tempdir_name, bool sho } std::string selfdir_name = proc_self_dirname(); - while (1) { - size_t pos = text.find(selfdir_name); - if (pos == std::string::npos) - break; - text = text.substr(0, pos) + "/" + text.substr(pos + GetSize(selfdir_name)); + if (selfdir_name != "/") { + while (1) { + size_t pos = text.find(selfdir_name); + if (pos == std::string::npos) + break; + text = text.substr(0, pos) + "/" + text.substr(pos + GetSize(selfdir_name)); + } } return text; From d9ef793430cf6bec2daeed20fbe44c3b060c435a Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Sat, 31 Mar 2018 14:50:21 -0700 Subject: [PATCH 082/184] Force abc to be linked statically and without threads in emscripten --- Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Makefile b/Makefile index b664cafc4..1a17bb857 100644 --- a/Makefile +++ b/Makefile @@ -178,6 +178,11 @@ EXE = .js TARGETS := $(filter-out yosys-config,$(TARGETS)) EXTRA_TARGETS += yosysjs-$(YOSYS_VER).zip +ifeq ($(ENABLE_ABC),1) +LINK_ABC := 1 +DISABLE_ABC_THREADS := 1 +endif + viz.js: wget -O viz.js.part https://github.com/mdaines/viz.js/releases/download/0.0.3/viz.js mv viz.js.part viz.js From 0abe7c6c77cdb4017cf5d8c34766e43806ce4876 Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Tue, 14 Nov 2017 04:09:32 -0800 Subject: [PATCH 083/184] Modify emscripten main to mount nodefs and to run arg as a script --- kernel/driver.cc | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/kernel/driver.cc b/kernel/driver.cc index bec872c24..178641101 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -85,20 +85,37 @@ USING_YOSYS_NAMESPACE #ifdef EMSCRIPTEN # include # include +# include extern "C" int main(int, char**); extern "C" void run(const char*); extern "C" const char *errmsg(); extern "C" const char *prompt(); -int main(int, char**) +int main(int argc, char **argv) { + EM_ASM( + if (ENVIRONMENT_IS_NODE) + { + FS.mkdir('/hostcwd'); + FS.mount(NODEFS, { root: '.' }, '/hostcwd'); + FS.mkdir('/hostfs'); + FS.mount(NODEFS, { root: '/' }, '/hostfs'); + } + ); + mkdir("/work", 0777); chdir("/work"); log_files.push_back(stdout); log_error_stderr = true; yosys_banner(); yosys_setup(); + + if (argc == 2) + { + // Run the first argument as a script file + run_frontend(argv[1], "script", 0, 0, 0); + } } void run(const char *command) From bea71e71ca4f2b756519cd67ec99d24f1e70b53b Mon Sep 17 00:00:00 2001 From: Robert Ou Date: Fri, 18 May 2018 22:45:43 -0700 Subject: [PATCH 084/184] Force abc to align memory to 8 bytes Apparently abc has a memory pool implementation that by default returns memory that is unaligned. There is a workaround in the abc makefile that uses uname to look for "arm" specifically and then sets the alignment. However, ARM is not the only platform that requires proper alignment (e.g. emscripten does too). For now, pessimistically force the alignment for 8 bytes all the time (somehow 4 wasn't enough for fixing emscripten despite being approximately a 32-bit platform). --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1a17bb857..ef838624a 100644 --- a/Makefile +++ b/Makefile @@ -164,7 +164,7 @@ else ifeq ($(CONFIG),emcc) CXX = emcc LD = emcc CXXFLAGS := -std=c++11 $(filter-out -fPIC -ggdb,$(CXXFLAGS)) -ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DABC_MEMALIGN=8" EMCCFLAGS := -Os -Wno-warn-absolute-paths EMCCFLAGS += --memory-init-file 0 --embed-file share -s NO_EXIT_RUNTIME=1 EMCCFLAGS += -s EXPORTED_FUNCTIONS="['_main','_run','_prompt','_errmsg']" From 4d645f0fce9e3af857cb292eca719c22141d379b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 May 2018 17:07:06 +0200 Subject: [PATCH 085/184] Fix verific handling of anyconst/anyseq attributes Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 41 +++++++++++++++++++++++------------- frontends/verific/verific.h | 3 ++- 2 files changed, 28 insertions(+), 16 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 624c04be9..7ebcbca04 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -189,12 +189,12 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn } } -RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst) +RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst, const pool *any_all_nets) { RTLIL::SigSpec sig; RTLIL::Wire *dummy_wire = NULL; for (int i = int(inst->OutputSize())-1; i >= 0; i--) - if (inst->GetOutputBit(i)) { + if (inst->GetOutputBit(i) && (!any_all_nets || !any_all_nets->count(inst->GetOutputBit(i)))) { sig.append(net_map_at(inst->GetOutputBit(i))); dummy_wire = NULL; } else { @@ -394,6 +394,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr #define IN1 operatorInput1(inst) #define IN2 operatorInput2(inst) #define OUT operatorOutput(inst) + #define FILTERED_OUT operatorOutput(inst, &any_all_nets) #define SIGNED inst->View()->IsSigned() if (inst->Type() == OPER_ADDER) { @@ -525,7 +526,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr } if (inst->Type() == OPER_WIDE_BUF) { - module->addPos(inst_name, IN, OUT, SIGNED); + module->addPos(inst_name, IN, FILTERED_OUT, SIGNED); return true; } @@ -791,6 +792,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se dict init_nets; pool anyconst_nets, anyseq_nets; pool allconst_nets, allseq_nets; + any_all_nets.clear(); FOREACH_NET_OF_NETLIST(nl, mi, net) { @@ -871,23 +873,30 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se const char *allconst_attr = net->GetAttValue("allconst"); const char *allseq_attr = net->GetAttValue("allseq"); - if (rand_const_attr != nullptr && (!strcmp(rand_const_attr, "1") || !strcmp(rand_const_attr, "'1'"))) + if (rand_const_attr != nullptr && (!strcmp(rand_const_attr, "1") || !strcmp(rand_const_attr, "'1'"))) { anyconst_nets.insert(net); - - else if (rand_attr != nullptr && (!strcmp(rand_attr, "1") || !strcmp(rand_attr, "'1'"))) + any_all_nets.insert(net); + } + else if (rand_attr != nullptr && (!strcmp(rand_attr, "1") || !strcmp(rand_attr, "'1'"))) { anyseq_nets.insert(net); - - else if (anyconst_attr != nullptr && (!strcmp(anyconst_attr, "1") || !strcmp(anyconst_attr, "'1'"))) + any_all_nets.insert(net); + } + else if (anyconst_attr != nullptr && (!strcmp(anyconst_attr, "1") || !strcmp(anyconst_attr, "'1'"))) { anyconst_nets.insert(net); - - else if (anyseq_attr != nullptr && (!strcmp(anyseq_attr, "1") || !strcmp(anyseq_attr, "'1'"))) + any_all_nets.insert(net); + } + else if (anyseq_attr != nullptr && (!strcmp(anyseq_attr, "1") || !strcmp(anyseq_attr, "'1'"))) { anyseq_nets.insert(net); - - else if (allconst_attr != nullptr && (!strcmp(allconst_attr, "1") || !strcmp(allconst_attr, "'1'"))) + any_all_nets.insert(net); + } + else if (allconst_attr != nullptr && (!strcmp(allconst_attr, "1") || !strcmp(allconst_attr, "'1'"))) { allconst_nets.insert(net); - - else if (allseq_attr != nullptr && (!strcmp(allseq_attr, "1") || !strcmp(allseq_attr, "'1'"))) + any_all_nets.insert(net); + } + else if (allseq_attr != nullptr && (!strcmp(allseq_attr, "1") || !strcmp(allseq_attr, "'1'"))) { allseq_nets.insert(net); + any_all_nets.insert(net); + } if (net_map.count(net)) { if (verific_verbose) @@ -1064,7 +1073,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se } if (inst->Type() == PRIM_BUF) { - module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); + auto outnet = inst->GetOutput(); + if (!anyconst_nets.count(outnet) && !anyseq_nets.count(outnet) && !allconst_nets.count(outnet) && !allseq_nets.count(outnet)) + module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet)); continue; } diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 2dd688e0d..714b7c82a 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -65,6 +65,7 @@ struct VerificImporter std::map net_map; std::map sva_posedge_map; + pool any_all_nets; bool mode_gates, mode_keep, mode_nosva, mode_names, mode_verific; bool mode_autocover; @@ -79,7 +80,7 @@ struct VerificImporter RTLIL::SigSpec operatorInput1(Verific::Instance *inst); RTLIL::SigSpec operatorInput2(Verific::Instance *inst); RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname); - RTLIL::SigSpec operatorOutput(Verific::Instance *inst); + RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool *any_all_nets = nullptr); bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name); bool import_netlist_instance_cells(Verific::Instance *inst, RTLIL::IdString inst_name); From 251562a4918576bd485bcdcc908c0ac780689a77 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 May 2018 18:13:38 +0200 Subject: [PATCH 086/184] Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 7ebcbca04..19273c69a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1393,7 +1393,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a return; } - if (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE) + while (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE) { net = inst->GetInput(); inst = net->Driver();; From 001c9f1d45749535452d082a7c92a17954b603b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 May 2018 15:41:45 +0200 Subject: [PATCH 087/184] Fix Verific handling of single-bit anyseq/anyconst wires Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 19273c69a..60fa6db3b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -244,7 +244,9 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr } if (inst->Type() == PRIM_BUF) { - module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); + auto outnet = inst->GetOutput(); + if (!any_all_nets.count(outnet)) + module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet)); return true; } @@ -1074,7 +1076,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == PRIM_BUF) { auto outnet = inst->GetOutput(); - if (!anyconst_nets.count(outnet) && !anyseq_nets.count(outnet) && !allconst_nets.count(outnet) && !allseq_nets.count(outnet)) + if (!any_all_nets.count(outnet)) module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet)); continue; } From 9a946c207fd4f5e18ce464e39d7d180c29ce5c23 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 May 2018 13:36:35 +0200 Subject: [PATCH 088/184] Add comment to VIPER #13453 work-around Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 60fa6db3b..12f2fdd7f 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1395,6 +1395,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a return; } + // Use while() instead of if() to work around VIPER #13453 while (inst != nullptr && inst->Type() == PRIM_SVA_POSEDGE) { net = inst->GetInput(); From 74efafc1cfd94949cc368b3ac5fa1476ce950f03 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 May 2018 16:42:06 +0200 Subject: [PATCH 089/184] Add some cleanup code to memory_nordff Signed-off-by: Clifford Wolf --- passes/memory/memory_nordff.cc | 66 +++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 28 deletions(-) diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc index 5f87e8b79..87ab7c623 100644 --- a/passes/memory/memory_nordff.cc +++ b/passes/memory/memory_nordff.cc @@ -61,49 +61,59 @@ struct MemoryNordffPass : public Pass { SigSpec rd_addr = cell->getPort("\\RD_ADDR"); SigSpec rd_data = cell->getPort("\\RD_DATA"); + SigSpec rd_clk = cell->getPort("\\RD_CLK"); + SigSpec rd_en = cell->getPort("\\RD_EN"); Const rd_clk_enable = cell->getParam("\\RD_CLK_ENABLE"); + Const rd_clk_polarity = cell->getParam("\\RD_CLK_POLARITY"); for (int i = 0; i < rd_ports; i++) { bool clk_enable = rd_clk_enable[i] == State::S1; - if (!clk_enable) - continue; - - bool clk_polarity = cell->getParam("\\RD_CLK_POLARITY")[i] == State::S1; - bool transparent = cell->getParam("\\RD_TRANSPARENT")[i] == State::S1; - - SigSpec clk = cell->getPort("\\RD_CLK")[i] ; - SigSpec en = cell->getPort("\\RD_EN")[i]; - Cell *c; - - if (transparent) + if (clk_enable) { - SigSpec sig_q = module->addWire(NEW_ID, abits); - SigSpec sig_d = rd_addr.extract(abits * i, abits); - rd_addr.replace(abits * i, sig_q); - if (en != State::S1) - sig_d = module->Mux(NEW_ID, sig_q, sig_d, en); - c = module->addDff(NEW_ID, clk, sig_d, sig_q, clk_polarity); - } - else - { - SigSpec sig_d = module->addWire(NEW_ID, width); - SigSpec sig_q = rd_data.extract(width * i, width); - rd_data.replace(width *i, sig_d); - if (en != State::S1) - sig_d = module->Mux(NEW_ID, sig_q, sig_d, en); - c = module->addDff(NEW_ID, clk, sig_d, sig_q, clk_polarity); + bool clk_polarity = cell->getParam("\\RD_CLK_POLARITY")[i] == State::S1; + bool transparent = cell->getParam("\\RD_TRANSPARENT")[i] == State::S1; + + SigSpec clk = cell->getPort("\\RD_CLK")[i] ; + SigSpec en = cell->getPort("\\RD_EN")[i]; + Cell *c; + + if (transparent) + { + SigSpec sig_q = module->addWire(NEW_ID, abits); + SigSpec sig_d = rd_addr.extract(abits * i, abits); + rd_addr.replace(abits * i, sig_q); + if (en != State::S1) + sig_d = module->Mux(NEW_ID, sig_q, sig_d, en); + c = module->addDff(NEW_ID, clk, sig_d, sig_q, clk_polarity); + } + else + { + SigSpec sig_d = module->addWire(NEW_ID, width); + SigSpec sig_q = rd_data.extract(width * i, width); + rd_data.replace(width *i, sig_d); + if (en != State::S1) + sig_d = module->Mux(NEW_ID, sig_q, sig_d, en); + c = module->addDff(NEW_ID, clk, sig_d, sig_q, clk_polarity); + } + + log("Extracted %s FF from read port %d of %s.%s: %s\n", transparent ? "addr" : "data", + i, log_id(module), log_id(cell), log_id(c)); } - log("Extracted %s FF from read port %d of %s.%s: %s\n", transparent ? "addr" : "data", - i, log_id(module), log_id(cell), log_id(c)); + rd_en[i] = State::S1; + rd_clk[i] = State::S0; rd_clk_enable[i] = State::S0; + rd_clk_polarity[i] = State::S1; } cell->setPort("\\RD_ADDR", rd_addr); cell->setPort("\\RD_DATA", rd_data); + cell->setPort("\\RD_CLK", rd_clk); + cell->setPort("\\RD_EN", rd_en); cell->setParam("\\RD_CLK_ENABLE", rd_clk_enable); + cell->setParam("\\RD_CLK_POLARITY", rd_clk_polarity); } } } MemoryNordffPass; From cee4b1e6bc11fff1d2d97985a96e6990afc57950 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 28 May 2018 17:16:15 +0200 Subject: [PATCH 090/184] Disable memory_dff for initialized FFs Signed-off-by: Clifford Wolf --- passes/memory/memory_dff.cc | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 40691d160..6e036397d 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -33,8 +33,20 @@ struct MemoryDffWorker dict sigbit_users_count; dict mux_cells_a, mux_cells_b; pool forward_merged_dffs, candidate_dffs; + pool init_bits; - MemoryDffWorker(Module *module) : module(module), sigmap(module) { } + MemoryDffWorker(Module *module) : module(module), sigmap(module) + { + for (auto wire : module->wires()) { + if (wire->attributes.count("\\init") == 0) + continue; + SigSpec sig = sigmap(wire); + Const initval = wire->attributes.count("\\init"); + for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++) + if (initval[i] == State::S0 || initval[i] == State::S1) + init_bits.insert(sig[i]); + } + } bool find_sig_before_dff(RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false) { @@ -45,6 +57,9 @@ struct MemoryDffWorker if (bit.wire == NULL) continue; + if (!after && init_bits.count(sigmap(bit))) + return false; + for (auto cell : dff_cells) { if (after && forward_merged_dffs.count(cell)) @@ -72,6 +87,9 @@ struct MemoryDffWorker if (d.size() != 1) continue; + if (after && init_bits.count(d)) + return false; + bit = d; clk = this_clk; clk_polarity = this_clk_polarity; From a77e27ab1579ed0f89bff898d0a0ea7ae0c13701 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 May 2018 13:04:40 +0200 Subject: [PATCH 091/184] Update ABC to git rev 6df1396 Signed-off-by: Clifford Wolf --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ef838624a..2db6612a7 100644 --- a/Makefile +++ b/Makefile @@ -106,7 +106,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = f23ea8e +ABCREV = 6df1396 ABCPULL = 1 ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 From 7fecc3c199e6cfe4b474431d54027d699bc8d343 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 May 2018 13:17:09 +0200 Subject: [PATCH 092/184] Make -nordff the default in "prep" Signed-off-by: Clifford Wolf --- techlibs/common/prep.cc | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc index 3dfc60383..cc977f97e 100644 --- a/techlibs/common/prep.cc +++ b/techlibs/common/prep.cc @@ -55,13 +55,14 @@ struct PrepPass : public ScriptPass log("\n"); log(" -memx\n"); log(" simulate verilog simulation behavior for out-of-bounds memory accesses\n"); - log(" using the 'memory_memx' pass. This option implies -nordff.\n"); + log(" using the 'memory_memx' pass.\n"); log("\n"); log(" -nomem\n"); log(" do not run any of the memory_* passes\n"); log("\n"); - log(" -nordff\n"); - log(" passed to 'memory_dff'. prohibits merging of FFs into memory read ports\n"); + log(" -rdff\n"); + log(" do not pass -nordff to 'memory_dff'. This enables merging of FFs into\n"); + log(" memory read ports.\n"); log("\n"); log(" -nokeepdc\n"); log(" do not call opt_* with -keepdc\n"); @@ -77,13 +78,12 @@ struct PrepPass : public ScriptPass log("\n"); } - string top_module, fsm_opts, memory_opts; - bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc; + string top_module, fsm_opts; + bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff; virtual void clear_flags() YS_OVERRIDE { top_module.clear(); - memory_opts.clear(); autotop = false; flatten = false; @@ -91,6 +91,7 @@ struct PrepPass : public ScriptPass memxmode = false; nomemmode = false; nokeepdc = false; + nordff = true; } virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -129,7 +130,6 @@ struct PrepPass : public ScriptPass } if (args[argidx] == "-memx") { memxmode = true; - memory_opts += " -nordff"; continue; } if (args[argidx] == "-nomem") { @@ -137,7 +137,11 @@ struct PrepPass : public ScriptPass continue; } if (args[argidx] == "-nordff") { - memory_opts += " -nordff"; + nordff = true; + continue; + } + if (args[argidx] == "-rdff") { + nordff = false; continue; } if (args[argidx] == "-nokeepdc") { @@ -196,7 +200,7 @@ struct PrepPass : public ScriptPass run(memxmode ? "wreduce -memx" : "wreduce"); } if (!nomemmode) { - run("memory_dff" + (help_mode ? " [-nordff]" : memory_opts)); + run(string("memory_dff") + (help_mode ? " [-nordff]" : nordff ? " -nordff" : "")); if (help_mode || memxmode) run("memory_memx", "(if -memx)"); run("opt_clean"); From 7f0548c16f64bd0c4e3bd85744cfdcf9494b4829 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 30 May 2018 14:17:36 +0200 Subject: [PATCH 093/184] Update examples/cmos/counter.ys to use "synth" command Signed-off-by: Clifford Wolf --- examples/cmos/counter.ys | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/cmos/counter.ys b/examples/cmos/counter.ys index a784f3465..d0b093667 100644 --- a/examples/cmos/counter.ys +++ b/examples/cmos/counter.ys @@ -1,11 +1,12 @@ - read_verilog counter.v read_verilog -lib cmos_cells.v -proc;; memory;; techmap;; - +synth dfflibmap -liberty cmos_cells.lib -abc -liberty cmos_cells.lib;; +abc -liberty cmos_cells.lib +opt_clean + +stat -liberty cmos_cells.lib # http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib # dfflibmap -liberty osu025_stdcells.lib @@ -13,4 +14,3 @@ abc -liberty cmos_cells.lib;; write_verilog synth.v write_spice synth.sp - From 3ab79a231b1b31f1177df2c1351643eda4e9553b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 May 2018 18:09:31 +0200 Subject: [PATCH 094/184] Bugfix in handling of array instances with empty ports Signed-off-by: Clifford Wolf --- passes/hierarchy/hierarchy.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 18dfa7184..bfb8e7f95 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -258,7 +258,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check if (mod->wires_.count(portname) == 0) log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); int port_size = mod->wires_.at(portname)->width; - if (conn_size == port_size) + if (conn_size == port_size || conn_size == 0) continue; if (conn_size != port_size*num) log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first)); From 4cd6d5556ade3a6da64d3639e6b6e547222820e8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Jun 2018 11:49:58 +0200 Subject: [PATCH 095/184] Add "setundef -anyconst" Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 61 +++++++++++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 20 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index c11ddbdc1..be26c3fd4 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -23,6 +23,13 @@ #include "kernel/rtlil.h" #include "kernel/log.h" +#define MODE_ZERO 0 +#define MODE_ONE 1 +#define MODE_UNDEF 2 +#define MODE_RANDOM 3 +#define MODE_ANYSEQ 4 +#define MODE_ANYCONST 5 + USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -34,30 +41,32 @@ struct SetundefWorker RTLIL::State next_bit() { - if (next_bit_mode == 0) + if (next_bit_mode == MODE_ZERO) return RTLIL::State::S0; - if (next_bit_mode == 1) + if (next_bit_mode == MODE_ONE) return RTLIL::State::S1; - if (next_bit_mode == 2) - log_abort(); - - if (next_bit_mode == 4) + if (next_bit_mode == MODE_UNDEF) return RTLIL::State::Sx; - // xorshift32 - next_bit_state ^= next_bit_state << 13; - next_bit_state ^= next_bit_state >> 17; - next_bit_state ^= next_bit_state << 5; - log_assert(next_bit_state != 0); + if (next_bit_mode == MODE_RANDOM) + { + // xorshift32 + next_bit_state ^= next_bit_state << 13; + next_bit_state ^= next_bit_state >> 17; + next_bit_state ^= next_bit_state << 5; + log_assert(next_bit_state != 0); - return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; + return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1; + } + + log_abort(); } void operator()(RTLIL::SigSpec &sig) { - if (next_bit_mode == 2) { + if (next_bit_mode == MODE_ANYSEQ || next_bit_mode == MODE_ANYCONST) { siglist.push_back(&sig); return; } @@ -93,6 +102,9 @@ struct SetundefPass : public Pass { log(" -anyseq\n"); log(" replace with $anyseq drivers (for formal)\n"); log("\n"); + log(" -anyconst\n"); + log(" replace with $anyconst drivers (for formal)\n"); + log("\n"); log(" -random \n"); log(" replace with random bits using the specified integer als seed\n"); log(" value for the random number generator.\n"); @@ -119,25 +131,31 @@ struct SetundefPass : public Pass { } if (args[argidx] == "-zero") { got_value = true; - worker.next_bit_mode = 0; + worker.next_bit_mode = MODE_ZERO; worker.next_bit_state = 0; continue; } if (args[argidx] == "-one") { got_value = true; - worker.next_bit_mode = 1; + worker.next_bit_mode = MODE_ONE; worker.next_bit_state = 0; continue; } if (args[argidx] == "-anyseq") { got_value = true; - worker.next_bit_mode = 2; + worker.next_bit_mode = MODE_ANYSEQ; + worker.next_bit_state = 0; + continue; + } + if (args[argidx] == "-anyconst") { + got_value = true; + worker.next_bit_mode = MODE_ANYCONST; worker.next_bit_state = 0; continue; } if (args[argidx] == "-undef") { got_value = true; - worker.next_bit_mode = 4; + worker.next_bit_mode = MODE_UNDEF; worker.next_bit_state = 0; continue; } @@ -147,7 +165,7 @@ struct SetundefPass : public Pass { } if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; - worker.next_bit_mode = 3; + worker.next_bit_mode = MODE_RANDOM; worker.next_bit_state = atoi(args[++argidx].c_str()) + 1; for (int i = 0; i < 10; i++) worker.next_bit(); @@ -274,7 +292,7 @@ struct SetundefPass : public Pass { module->rewrite_sigspecs(worker); - if (worker.next_bit_mode == 2) + if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST) { vector siglist; siglist.swap(worker.siglist); @@ -291,7 +309,10 @@ struct SetundefPass : public Pass { width++; if (width > 0) { - sig.replace(cursor, module->Anyseq(NEW_ID, width)); + if (worker.next_bit_mode == MODE_ANYSEQ) + sig.replace(cursor, module->Anyseq(NEW_ID, width)); + else + sig.replace(cursor, module->Anyconst(NEW_ID, width)); cursor += width; } else { cursor++; From f273291dfe5de460192ef2a63a121b3c2e8b9a62 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Jun 2018 11:57:28 +0200 Subject: [PATCH 096/184] Add setundef -anyseq / -anyconst support to -undriven mode Signed-off-by: Clifford Wolf --- passes/cmds/setundef.cc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index be26c3fd4..3a3ebedf1 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -176,7 +176,10 @@ struct SetundefPass : public Pass { extra_args(args, argidx, design); if (!got_value) - log_cmd_error("One of the options -zero, -one, -anyseq, or -random must be specified.\n"); + log_cmd_error("One of the options -zero, -one, -anyseq, -anyconst, or -random must be specified.\n"); + + if (init_mode && (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)) + log_cmd_error("The options -init and -anyseq / -anyconst are exclusive.\n"); for (auto module : design->selected_modules()) { @@ -204,8 +207,13 @@ struct SetundefPass : public Pass { RTLIL::SigSpec sig = undriven_signals.export_all(); for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; - for (int i = 0; i < c.width; i++) - bits.append(worker.next_bit()); + if (worker.next_bit_mode == MODE_ANYSEQ) + bits = module->Anyseq(NEW_ID, c.width); + else if (worker.next_bit_mode == MODE_ANYCONST) + bits = module->Anyconst(NEW_ID, c.width); + else + for (int i = 0; i < c.width; i++) + bits.append(worker.next_bit()); module->connect(RTLIL::SigSig(c, bits)); } } From 4372cf690d829755279a6a5778023e5e0a4493b2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Jun 2018 13:25:42 +0200 Subject: [PATCH 097/184] Add (* gclk *) attribute support Signed-off-by: Clifford Wolf --- README.md | 4 +++- frontends/ast/genrtlil.cc | 9 +++++++++ frontends/verific/verific.cc | 10 ++++++++++ frontends/verific/verific.h | 1 + 4 files changed, 23 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 704948e2d..c02691d94 100644 --- a/README.md +++ b/README.md @@ -418,7 +418,9 @@ Non-standard or SystemVerilog features for formal verification supported in any clocked block. - The syntax ``@($global_clock)`` can be used to create FFs that have no - explicit clock input ($ff cells). + explicit clock input ($ff cells). The same can be achieved by using + ``@(posedge )`` or ``@(negedge )`` when ```` + is marked with the ``(* gclk *)`` Verilog attribute. Supported features from SystemVerilog diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 57ba9668d..40cbbc2a3 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -223,12 +223,18 @@ struct AST_INTERNAL::ProcessGenerator bool found_global_syncs = false; bool found_anyedge_syncs = false; for (auto child : always->children) + { + if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && + child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) { + found_global_syncs = true; + } if (child->type == AST_EDGE) { if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->str == "\\$global_clock") found_global_syncs = true; else found_anyedge_syncs = true; } + } if (found_anyedge_syncs) { if (found_global_syncs) @@ -242,6 +248,9 @@ struct AST_INTERNAL::ProcessGenerator bool found_clocked_sync = false; for (auto child : always->children) if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) { + if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast && + child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) + continue; found_clocked_sync = true; if (found_global_syncs || found_anyedge_syncs) log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 12f2fdd7f..f67337754 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1470,6 +1470,10 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a clock_net = net; clock_sig = importer->net_map_at(clock_net); + + const char *gclk_attr = clock_net->GetAttValue("gclk"); + if (gclk_attr != nullptr && (!strcmp(gclk_attr, "1") || !strcmp(gclk_attr, "'1'"))) + gclk = true; } Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value) @@ -1492,15 +1496,20 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const sig_d = module->Mux(NEW_ID, sig_q, sig_d, enable_sig); if (disable_sig != State::S0) { + log_assert(gclk == false); log_assert(GetSize(sig_q) == GetSize(init_value)); return module->addAdff(name, clock_sig, disable_sig, sig_d, sig_q, init_value, posedge); } + if (gclk) + return module->addFf(name, sig_d, sig_q); + return module->addDff(name, clock_sig, sig_d, sig_q, posedge); } Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value) { + log_assert(gclk == false); log_assert(disable_sig == State::S0); if (enable_sig != State::S1) @@ -1511,6 +1520,7 @@ Cell *VerificClocking::addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec s Cell *VerificClocking::addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q) { + log_assert(gclk == false); log_assert(disable_sig == State::S0); if (enable_sig != State::S1) diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 714b7c82a..86a743ea1 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -40,6 +40,7 @@ struct VerificClocking { SigBit enable_sig = State::S1; SigBit disable_sig = State::S0; bool posedge = true; + bool gclk = false; VerificClocking() { } VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false); From 106af19b69c1a62531655d35f5a8f3f7eda838e7 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Tue, 5 Jun 2018 17:52:36 +0300 Subject: [PATCH 098/184] Fixed typo (sikp -> skip) --- tests/tools/autotest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 31a6ae8ab..d6216244f 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -100,7 +100,7 @@ do echo -n "Test: $bn " fi - rm -f ${bn}.{err,log,sikp} + rm -f ${bn}.{err,log,skip} mkdir -p ${bn}.out rm -rf ${bn}.out/* From 8b7580b0a152ec937abb1510abf5f2d7cd3b7acb Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Wed, 6 Jun 2018 22:27:25 +0300 Subject: [PATCH 099/184] Detect illegal port declaration, e.g input/output/inout keyword must be the first. --- frontends/verilog/verilog_parser.y | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e803d8072..72a501d11 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -376,9 +376,10 @@ wire_type: }; wire_type_token_list: - wire_type_token | wire_type_token_list wire_type_token; + wire_type_token | wire_type_token_list wire_type_token | + wire_type_token_io ; -wire_type_token: +wire_type_token_io: TOK_INPUT { astbuf3->is_input = true; } | @@ -388,7 +389,9 @@ wire_type_token: TOK_INOUT { astbuf3->is_input = true; astbuf3->is_output = true; - } | + }; + +wire_type_token: TOK_WIRE { } | TOK_REG { From 83631555dd5d57e2a3d3b7175f77baf0ad67ccd9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 11 Jun 2018 18:10:12 +0200 Subject: [PATCH 100/184] Fix ice40_opt for cases where a port is connected to a signal with width != 1 Signed-off-by: Clifford Wolf --- techlibs/ice40/ice40_opt.cc | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index ae72f5d64..7af60f297 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -26,6 +26,13 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +static SigBit get_bit_or_zero(const SigSpec &sig) +{ + if (GetSize(sig) == 0) + return State::S0; + return sig[0]; +} + static void run_ice40_opts(Module *module, bool unlut_mode) { pool optimized_co; @@ -45,7 +52,11 @@ static void run_ice40_opts(Module *module, bool unlut_mode) SigSpec non_const_inputs, replacement_output; int count_zeros = 0, count_ones = 0; - SigBit inbit[3] = {cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\CI")}; + SigBit inbit[3] = { + get_bit_or_zero(cell->getPort("\\I0")), + get_bit_or_zero(cell->getPort("\\I1")), + get_bit_or_zero(cell->getPort("\\CI")) + }; for (int i = 0; i < 3; i++) if (inbit[i].wire == nullptr) { if (inbit[i] == State::S1) @@ -63,8 +74,8 @@ static void run_ice40_opts(Module *module, bool unlut_mode) replacement_output = non_const_inputs; if (GetSize(replacement_output)) { - optimized_co.insert(sigmap(cell->getPort("\\CO"))); - module->connect(cell->getPort("\\CO"), replacement_output); + optimized_co.insert(sigmap(cell->getPort("\\CO")[0])); + module->connect(cell->getPort("\\CO")[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); log("Optimized away SB_CARRY cell %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); @@ -78,10 +89,10 @@ static void run_ice40_opts(Module *module, bool unlut_mode) { SigSpec inbits; - inbits.append(cell->getPort("\\I0")); - inbits.append(cell->getPort("\\I1")); - inbits.append(cell->getPort("\\I2")); - inbits.append(cell->getPort("\\I3")); + inbits.append(get_bit_or_zero(cell->getPort("\\I0"))); + inbits.append(get_bit_or_zero(cell->getPort("\\I1"))); + inbits.append(get_bit_or_zero(cell->getPort("\\I2"))); + inbits.append(get_bit_or_zero(cell->getPort("\\I3"))); sigmap.apply(inbits); if (unlut_mode) @@ -104,8 +115,13 @@ static void run_ice40_opts(Module *module, bool unlut_mode) cell->setParam("\\LUT", cell->getParam("\\LUT_INIT")); cell->unsetParam("\\LUT_INIT"); - cell->setPort("\\A", SigSpec({cell->getPort("\\I3"), cell->getPort("\\I2"), cell->getPort("\\I1"), cell->getPort("\\I0")})); - cell->setPort("\\Y", cell->getPort("\\O")); + cell->setPort("\\A", SigSpec({ + get_bit_or_zero(cell->getPort("\\I3")), + get_bit_or_zero(cell->getPort("\\I2")), + get_bit_or_zero(cell->getPort("\\I1")), + get_bit_or_zero(cell->getPort("\\I0")) + })); + cell->setPort("\\Y", cell->getPort("\\O")[0]); cell->unsetPort("\\I0"); cell->unsetPort("\\I1"); cell->unsetPort("\\I2"); From 57fc8dd58229d309ba56b374223802936444ecd4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Jun 2018 13:35:10 +0200 Subject: [PATCH 101/184] Add "synth_ice40 -json" Signed-off-by: Clifford Wolf --- techlibs/ice40/synth_ice40.cc | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 177581d53..abd890a56 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -45,7 +45,11 @@ struct SynthIce40Pass : public ScriptPass log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -edif \n"); - log(" write the design to the specified edif file. writing of an output file\n"); + log(" write the design to the specified EDIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -run :\n"); @@ -81,7 +85,7 @@ struct SynthIce40Pass : public ScriptPass log("\n"); } - string top_opt, blif_file, edif_file; + string top_opt, blif_file, edif_file, json_file; bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr; virtual void clear_flags() YS_OVERRIDE @@ -89,6 +93,7 @@ struct SynthIce40Pass : public ScriptPass top_opt = "-auto-top"; blif_file = ""; edif_file = ""; + json_file = ""; nocarry = false; nodffe = false; nobram = false; @@ -118,6 +123,10 @@ struct SynthIce40Pass : public ScriptPass edif_file = args[++argidx]; continue; } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -260,17 +269,15 @@ struct SynthIce40Pass : public ScriptPass if (!blif_file.empty() || help_mode) { if (vpr || help_mode) { run(stringf("opt_clean -purge"), - " " - " (vpr mode)"); + " (vpr mode)"); run(stringf("write_blif -attr -cname -conn -param %s", - help_mode ? "" : blif_file.c_str()), - " (vpr mode)"); + help_mode ? "" : blif_file.c_str()), + " (vpr mode)"); } if (!vpr) run(stringf("write_blif -gates -attr -param %s", - help_mode ? "" : blif_file.c_str()), - " " - " (non-vpr mode)"); + help_mode ? "" : blif_file.c_str()), + " (non-vpr mode)"); } } @@ -279,6 +286,12 @@ struct SynthIce40Pass : public ScriptPass if (!edif_file.empty() || help_mode) run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + } } } SynthIce40Pass; From 0ff0ce4973db6f91b717b3771d8a9ca4cdb3a191 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 15 Jun 2018 18:56:44 +0200 Subject: [PATCH 102/184] Bugfix in liberty parser (as suggested by aiju in #569) Signed-off-by: Clifford Wolf --- frontends/liberty/liberty.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index c9b6a54b2..b9e53a4be 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -148,7 +148,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top && stack[top].type == 2) { - if (next_token.type == '*' || next_token.type == '&' || next_token.type == 0 || next_token.type == '(') + if (next_token.type == '*' || next_token.type == '&' || next_token.type == 0 || next_token.type == '(' || next_token.type == '!') return false; stack[top].type = 3; return true; From d89560a0ba6402a8d13177909cc2c1f3b8b7c3e2 Mon Sep 17 00:00:00 2001 From: Edmond Cote Date: Mon, 18 Jun 2018 17:29:01 -0700 Subject: [PATCH 103/184] Include module name for area summary stats The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~ --- passes/cmds/stat.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index e52a192db..f1d958a1a 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -142,7 +142,7 @@ struct statdata_t } } - void log_data() + void log_data(RTLIL::IdString mod_name, bool top_mod) { log(" Number of wires: %6d\n", num_wires); log(" Number of wire bits: %6d\n", num_wire_bits); @@ -163,7 +163,7 @@ struct statdata_t if (area != 0) { log("\n"); - log(" Chip area for this module: %f\n", area); + log(" Chip area for %smodule '%s': %f\n", (top_mod) ? "top " : "", mod_name.c_str(), area); } } }; @@ -275,7 +275,7 @@ struct StatPass : public Pass { log("\n"); log("=== %s%s ===\n", RTLIL::id2cstr(mod->name), design->selected_whole_module(mod->name) ? "" : " (partially selected)"); log("\n"); - data.log_data(); + data.log_data(mod->name, false); } if (top_mod != NULL && GetSize(mod_stat) > 1) @@ -288,7 +288,7 @@ struct StatPass : public Pass { statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0); log("\n"); - data.log_data(); + data.log_data(top_mod->name, true); } log("\n"); From 675a44b41a2df2c02ceccda2434bc3efac3e5e2f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 19 Jun 2018 14:29:38 +0200 Subject: [PATCH 104/184] Be slightly less aggressive in "deminout" pass Signed-off-by: Clifford Wolf --- passes/techmap/deminout.cc | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index ed4e45762..0b8fd5246 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -57,7 +57,7 @@ struct DeminoutPass : public Pass { for (auto module : design->selected_modules()) { SigMap sigmap(module); - pool bits_written, bits_used, bits_inout; + pool bits_written, bits_used, bits_inout, bits_tribuf; dict bits_numports; for (auto wire : module->wires()) @@ -82,6 +82,25 @@ struct DeminoutPass : public Pass { if (cellport_in) for (auto bit : sigmap(conn.second)) bits_used.insert(bit); + + if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_")) + { + bool tribuf = (cell->type == "$_TBUF_"); + + if (!tribuf) { + for (auto &c : cell->connections()) { + if (!c.first.in("\\A", "\\B")) + continue; + for (auto b : sigmap(c.second)) + if (b == State::Sz) + tribuf = true; + } + } + + if (tribuf) + for (auto bit : sigmap(conn.second)) + bits_tribuf.insert(bit); + } } for (auto wire : module->selected_wires()) @@ -95,10 +114,15 @@ struct DeminoutPass : public Pass { if (bits_numports[bit] > 1 || bits_inout.count(bit)) new_input = true, new_output = true; - if (bits_written.count(bit)) + if (bits_written.count(bit)) { new_output = true; - else if (bits_used.count(bit)) - new_input = true; + if (bits_tribuf.count(bit)) + goto tribuf_bit; + } else { + tribuf_bit: + if (bits_used.count(bit)) + new_input = true; + } } if (new_input != new_output) { From 53e9a1549c503492820b3672331950fd0a580ef0 Mon Sep 17 00:00:00 2001 From: Serge Bazanski Date: Tue, 19 Jun 2018 13:34:56 +0100 Subject: [PATCH 105/184] Add Protobuf backend Signed-off-by: Serge Bazanski --- Makefile | 5 + backends/protobuf/.gitignore | 2 + backends/protobuf/Makefile.inc | 8 + backends/protobuf/protobuf.cc | 370 +++++++++++++++++++++++++++++++++ misc/yosys.proto | 175 ++++++++++++++++ 5 files changed, 560 insertions(+) create mode 100644 backends/protobuf/.gitignore create mode 100644 backends/protobuf/Makefile.inc create mode 100644 backends/protobuf/protobuf.cc create mode 100644 misc/yosys.proto diff --git a/Makefile b/Makefile index 2db6612a7..11803ec0a 100644 --- a/Makefile +++ b/Makefile @@ -15,6 +15,7 @@ ENABLE_EDITLINE := 0 ENABLE_VERIFIC := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 +ENABLE_PROTOBUF := 0 # other configuration flags ENABLE_GPROF := 0 @@ -325,6 +326,10 @@ CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABL LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -lz endif +ifeq ($(ENABLE_PROTOBUF),1) +LDLIBS += $(shell pkg-config --cflags --libs protobuf) +endif + ifeq ($(ENABLE_COVER),1) CXXFLAGS += -DYOSYS_ENABLE_COVER endif diff --git a/backends/protobuf/.gitignore b/backends/protobuf/.gitignore new file mode 100644 index 000000000..849b38d45 --- /dev/null +++ b/backends/protobuf/.gitignore @@ -0,0 +1,2 @@ +yosys.pb.cc +yosys.pb.h diff --git a/backends/protobuf/Makefile.inc b/backends/protobuf/Makefile.inc new file mode 100644 index 000000000..a6e3c5ab7 --- /dev/null +++ b/backends/protobuf/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(ENABLE_PROTOBUF),1) + +backends/protobuf/yosys.pb.cc backends/protobuf/yosys.pb.h: share/yosys.proto + $(Q) cd misc && protoc --cpp_out "../backends/protobuf" yosys.proto + +OBJS += backends/protobuf/protobuf.o backends/protobuf/yosys.pb.o + +endif diff --git a/backends/protobuf/protobuf.cc b/backends/protobuf/protobuf.cc new file mode 100644 index 000000000..9a6fedee7 --- /dev/null +++ b/backends/protobuf/protobuf.cc @@ -0,0 +1,370 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2018 Serge Bazanski + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include + +#include "kernel/rtlil.h" +#include "kernel/register.h" +#include "kernel/sigtools.h" +#include "kernel/celltypes.h" +#include "kernel/cellaigs.h" +#include "kernel/log.h" +#include "yosys.pb.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct ProtobufDesignSerializer +{ + bool aig_mode_; + bool use_selection_; + yosys::pb::Design *pb_; + + Design *design_; + Module *module_; + + SigMap sigmap_; + int sigidcounter_; + dict sigids_; + pool aig_models_; + + + ProtobufDesignSerializer(bool use_selection, bool aig_mode) : + aig_mode_(aig_mode), use_selection_(use_selection) { } + + string get_name(IdString name) + { + return RTLIL::unescape_id(name); + } + + + void serialize_parameters(google::protobuf::Map *out, + const dict ¶meters) + { + for (auto ¶m : parameters) { + std::string key = get_name(param.first); + + + yosys::pb::Parameter pb_param; + + if ((param.second.flags & RTLIL::ConstFlags::CONST_FLAG_STRING) != 0) { + pb_param.set_str(param.second.decode_string()); + } else if (GetSize(param.second.bits) > 64) { + pb_param.set_str(param.second.as_string()); + } else { + pb_param.set_int_(param.second.as_int()); + } + + (*out)[key] = pb_param; + } + } + + void get_bits(yosys::pb::BitVector *out, SigSpec sig) + { + for (auto bit : sigmap_(sig)) { + auto sig = out->add_signal(); + + // Constant driver. + if (bit.wire == nullptr) { + if (bit == State::S0) sig->set_constant(sig->CONSTANT_DRIVER_LOW); + else if (bit == State::S1) sig->set_constant(sig->CONSTANT_DRIVER_HIGH); + else if (bit == State::Sz) sig->set_constant(sig->CONSTANT_DRIVER_Z); + else sig->set_constant(sig->CONSTANT_DRIVER_X); + continue; + } + + // Signal - give it a unique identifier. + if (sigids_.count(bit) == 0) { + sigids_[bit] = sigidcounter_++; + } + sig->set_id(sigids_[bit]); + } + } + + void serialize_module(yosys::pb::Module* out, Module *module) + { + module_ = module; + log_assert(module_->design == design_); + sigmap_.set(module_); + sigids_.clear(); + sigidcounter_ = 0; + + serialize_parameters(out->mutable_attribute(), module_->attributes); + + for (auto n : module_->ports) { + Wire *w = module->wire(n); + if (use_selection_ && !module_->selected(w)) + continue; + + yosys::pb::Module::Port pb_port; + pb_port.set_direction(w->port_input ? w->port_output ? + yosys::pb::DIRECTION_INOUT : yosys::pb::DIRECTION_INPUT : yosys::pb::DIRECTION_OUTPUT); + get_bits(pb_port.mutable_bits(), w); + (*out->mutable_port())[get_name(n)] = pb_port; + } + + for (auto c : module_->cells()) { + if (use_selection_ && !module_->selected(c)) + continue; + + yosys::pb::Module::Cell pb_cell; + pb_cell.set_hide_name(c->name[0] == '$'); + pb_cell.set_type(get_name(c->type)); + + if (aig_mode_) { + Aig aig(c); + if (aig.name.empty()) + continue; + pb_cell.set_model(aig.name); + aig_models_.insert(aig); + } + serialize_parameters(pb_cell.mutable_parameter(), c->parameters); + serialize_parameters(pb_cell.mutable_attribute(), c->attributes); + + if (c->known()) { + for (auto &conn : c->connections()) { + yosys::pb::Direction direction = yosys::pb::DIRECTION_OUTPUT; + if (c->input(conn.first)) + direction = c->output(conn.first) ? yosys::pb::DIRECTION_INOUT : yosys::pb::DIRECTION_INPUT; + (*pb_cell.mutable_port_direction())[get_name(conn.first)] = direction; + } + } + for (auto &conn : c->connections()) { + yosys::pb::BitVector vec; + get_bits(&vec, conn.second); + (*pb_cell.mutable_connection())[get_name(conn.first)] = vec; + } + + (*out->mutable_cell())[get_name(c->name)] = pb_cell; + } + + for (auto w : module_->wires()) { + if (use_selection_ && !module_->selected(w)) + continue; + + auto netname = out->add_netname(); + netname->set_hide_name(w->name[0] == '$'); + get_bits(netname->mutable_bits(), w); + serialize_parameters(netname->mutable_attributes(), w->attributes); + } + } + + + void serialize_models(google::protobuf::Map *models) + { + for (auto &aig : aig_models_) { + yosys::pb::Model pb_model; + for (auto &node : aig.nodes) { + auto pb_node = pb_model.add_node(); + if (node.portbit >= 0) { + if (node.inverter) { + pb_node->set_type(pb_node->TYPE_NPORT); + } else { + pb_node->set_type(pb_node->TYPE_PORT); + } + auto port = pb_node->mutable_port(); + port->set_portname(log_id(node.portname)); + port->set_bitindex(node.portbit); + } else if (node.left_parent < 0 && node.right_parent < 0) { + if (node.inverter) { + pb_node->set_type(pb_node->TYPE_TRUE); + } else { + pb_node->set_type(pb_node->TYPE_FALSE); + } + } else { + if (node.inverter) { + pb_node->set_type(pb_node->TYPE_NAND); + } else { + pb_node->set_type(pb_node->TYPE_AND); + } + auto gate = pb_node->mutable_gate(); + gate->set_left(node.left_parent); + gate->set_right(node.right_parent); + } + for (auto &op : node.outports) { + auto pb_op = pb_node->add_out_port(); + pb_op->set_name(log_id(op.first)); + pb_op->set_bit_index(op.second); + } + } + (*models)[aig.name] = pb_model; + } + } + + void serialize_design(yosys::pb::Design *pb, Design *design) + { + GOOGLE_PROTOBUF_VERIFY_VERSION; + pb_ = pb; + pb_->Clear(); + pb_->set_creator(yosys_version_str); + + design_ = design; + design_->sort(); + + auto modules = use_selection_ ? design_->selected_modules() : design_->modules(); + for (auto mod : modules) { + yosys::pb::Module pb_mod; + serialize_module(&pb_mod, mod); + (*pb->mutable_modules())[mod->name.str()] = pb_mod; + } + + serialize_models(pb_->mutable_models()); + } +}; + +struct ProtobufBackend : public Backend { + ProtobufBackend(): Backend("protobuf", "write design to a Protocol Buffer file") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" write_protobuf [options] [filename]\n"); + log("\n"); + log("Write a JSON netlist of the current design.\n"); + log("\n"); + log(" -aig\n"); + log(" include AIG models for the different gate types\n"); + log("\n"); + log(" -text\n"); + log(" output protobuf in Text/ASCII representation\n"); + log("\n"); + log("The schema of the output Protocol Buffer is defined in misc/yosys.pb in the\n"); + log("Yosys source code distribution.\n"); + log("\n"); + } + virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + { + bool aig_mode = false; + bool text_mode = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-aig") { + aig_mode = true; + continue; + } + if (args[argidx] == "-text") { + text_mode = true; + continue; + } + break; + } + extra_args(f, filename, args, argidx); + + log_header(design, "Executing Protobuf backend.\n"); + + yosys::pb::Design pb; + ProtobufDesignSerializer serializer(false, aig_mode); + serializer.serialize_design(&pb, design); + + if (text_mode) { + string out; + google::protobuf::TextFormat::PrintToString(pb, &out); + *f << out; + } else { + pb.SerializeToOstream(f); + } + } +} ProtobufBackend; + +struct ProtobufPass : public Pass { + ProtobufPass() : Pass("protobuf", "write design in Protobuf format") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" protobuf [options] [selection]\n"); + log("\n"); + log("Write a JSON netlist of all selected objects.\n"); + log("\n"); + log(" -o \n"); + log(" write to the specified file.\n"); + log("\n"); + log(" -aig\n"); + log(" include AIG models for the different gate types\n"); + log("\n"); + log(" -text\n"); + log(" output protobuf in Text/ASCII representation\n"); + log("\n"); + log("The schema of the output Protocol Buffer is defined in misc/yosys.pb in the\n"); + log("Yosys source code distribution.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + std::string filename; + bool aig_mode = false; + bool text_mode = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-o" && argidx+1 < args.size()) { + filename = args[++argidx]; + continue; + } + if (args[argidx] == "-aig") { + aig_mode = true; + continue; + } + if (args[argidx] == "-text") { + text_mode = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + std::ostream *f; + std::stringstream buf; + + if (!filename.empty()) { + std::ofstream *ff = new std::ofstream; + ff->open(filename.c_str(), std::ofstream::trunc); + if (ff->fail()) { + delete ff; + log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + } + f = ff; + } else { + f = &buf; + } + + yosys::pb::Design pb; + ProtobufDesignSerializer serializer(true, aig_mode); + serializer.serialize_design(&pb, design); + + if (text_mode) { + string out; + google::protobuf::TextFormat::PrintToString(pb, &out); + *f << out; + } else { + pb.SerializeToOstream(f); + } + + if (!filename.empty()) { + delete f; + } else { + log("%s", buf.str().c_str()); + } + } +} ProtobufPass; + +PRIVATE_NAMESPACE_END; diff --git a/misc/yosys.proto b/misc/yosys.proto new file mode 100644 index 000000000..2870176cb --- /dev/null +++ b/misc/yosys.proto @@ -0,0 +1,175 @@ +// +// yosys -- Yosys Open SYnthesis Suite +// +// Copyright (C) 2018 Serge Bazanski +// +// Permission to use, copy, modify, and/or distribute this software for any +// purpose with or without fee is hereby granted, provided that the above +// copyright notice and this permission notice appear in all copies. +// +// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// + +/// Protobuf definition of Yosys RTLIL dump/restore format for RTL designs. + +syntax = "proto3"; + +package yosys.pb; + +// Port direction. +enum Direction { + DIRECTION_INVALID = 0; + DIRECTION_INPUT = 1; + DIRECTION_OUTPUT = 2; + DIRECTION_INOUT = 3; +} + +// A freeform parameter/attribute value. +message Parameter { + oneof value { + int64 int = 1; + string str = 2; + } +} + +// A signal in the design - either a unique identifier for one, or a constant +// driver (low or high). +message Signal { + // A constant signal driver in the design. + enum ConstantDriver { + CONSTANT_DRIVER_INVALID = 0; + CONSTANT_DRIVER_LOW = 1; + CONSTANT_DRIVER_HIGH = 2; + CONSTANT_DRIVER_Z = 3; + CONSTANT_DRIVER_X = 4; + } + oneof type { + // Signal uniquely identified by ID number. + int64 id = 1; + // Constant driver. + ConstantDriver constant = 2; + } +} + +// A vector of signals. +message BitVector { + repeated Signal signal = 1; +} + +// A netlist module. +message Module { + // Freeform attributes. + map attribute = 1; + + // Named ports in this module. + message Port { + Direction direction = 1; + BitVector bits = 2; + } + map port = 2; + + // Named cells in this module. + message Cell { + // Set to true when the name of this cell is automatically created and + // likely not of interest for a regular user. + bool hide_name = 1; + string type = 2; + // Set if this module has an AIG model available. + string model = 3; + // Freeform parameters. + map parameter = 4; + // Freeform attributes. + map attribute = 5; + + /// Ports of the cell. + // Direction of the port, if interface is known. + map port_direction = 6; + // Connection of named port to signal(s). + map connection = 7; + } + map cell = 3; + + // Nets in this module. + message Netname { + // Set to true when the name of this net is automatically created and + // likely not of interest for a regular user. + bool hide_name = 1; + // Signal(s) that make up this net. + BitVector bits = 2; + // Freeform attributes. + map attributes = 3; + } + repeated Netname netname = 4; +} + +// And-Inverter-Graph model. +message Model { + message Node { + // Type of AIG node - or, what its' value is. + enum Type { + TYPE_INVALID = 0; + // The node's value is the value of the specified input port bit. + TYPE_PORT = 1; + // The node's value is the inverted value of the specified input + // port bit. + TYPE_NPORT = 2; + // The node's value is the ANDed value of specified nodes. + TYPE_AND = 3; + // The node's value is the NANDed value of specified nodes. + TYPE_NAND = 4; + // The node's value is a constant 1. + TYPE_TRUE = 5; + // The node's value is a constant 0. + TYPE_FALSE = 6; + }; + Type type = 1; + + message Port { + // Name of port. + string portname = 1; + // Bit index in port. + int64 bitindex = 2; + } + message Gate { + // Node index of left side of operation. + int64 left = 1; + // Node index of right side of operation. + int64 right = 2; + } + oneof node { + // Set for PORT, NPORT + Port port = 2; + // Set for AND, NAND. + Gate gate = 3; + } + + // Set when the node drives given output port(s). + message OutPort { + // Name of port. + string name = 1; + // Bit index in port. + int64 bit_index = 2; + } + repeated OutPort out_port = 4; + } + + // List of AIG nodes - each is explicitely numbered by its' index in this + // array. + repeated Node node = 1; +} + +// A Yosys design netlist dumped from RTLIL. +message Design { + // Human-readable freeform 'remark' string. + string creator = 1; + // List of named modules in design. + map modules = 2; + // List of named AIG models in design (if AIG export enabled). + map models = 3; +} From 1690dafde135c1077d84cb14c1275d74a2f7424d Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Wed, 20 Jun 2018 19:28:43 +0100 Subject: [PATCH 106/184] Fix protobuf build --- backends/protobuf/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/protobuf/Makefile.inc b/backends/protobuf/Makefile.inc index a6e3c5ab7..834cad42c 100644 --- a/backends/protobuf/Makefile.inc +++ b/backends/protobuf/Makefile.inc @@ -1,6 +1,6 @@ ifeq ($(ENABLE_PROTOBUF),1) -backends/protobuf/yosys.pb.cc backends/protobuf/yosys.pb.h: share/yosys.proto +backends/protobuf/yosys.pb.cc backends/protobuf/yosys.pb.h: misc/yosys.proto $(Q) cd misc && protoc --cpp_out "../backends/protobuf" yosys.proto OBJS += backends/protobuf/protobuf.o backends/protobuf/yosys.pb.o From 5f2bc1ce7672324370ce5570f41ebd74f670b26e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 20 Jun 2018 23:45:01 +0200 Subject: [PATCH 107/184] Add automatic verific import in hierarchy command Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 53 +++++++++++++++++++++++++++++++++++ frontends/verific/verific.h | 3 ++ passes/hierarchy/hierarchy.cc | 20 ++++++++++++- 3 files changed, 75 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f67337754..ab5c545a1 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -62,6 +62,7 @@ using namespace Verific; YOSYS_NAMESPACE_BEGIN int verific_verbose; +bool verific_import_pending; string verific_error_msg; void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args) @@ -1613,6 +1614,52 @@ struct VerificExtNets } }; +void verific_import(Design *design, std::string top) +{ + std::set nl_todo, nl_done; + + { + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); + VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1); + + Array veri_libs, vhdl_libs; + if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); + if (veri_lib) veri_libs.InsertLast(veri_lib); + + Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs); + Netlist *nl; + int i; + + FOREACH_ARRAY_ITEM(netlists, i, nl) { + if (top.empty() || nl->Owner()->Name() == top) + nl_todo.insert(nl); + } + + delete netlists; + } + + if (!verific_error_msg.empty()) + log_error("%s\n", verific_error_msg.c_str()); + + while (!nl_todo.empty()) { + Netlist *nl = *nl_todo.begin(); + if (nl_done.count(nl) == 0) { + VerificImporter importer(false, false, false, false, false, false); + importer.import_netlist(design, nl, nl_todo); + } + nl_todo.erase(nl); + nl_done.insert(nl); + } + + veri_file::Reset(); + vhdl_file::Reset(); + Libset::Reset(); + verific_import_pending = false; + + if (!verific_error_msg.empty()) + log_error("%s\n", verific_error_msg.c_str()); +} + YOSYS_NAMESPACE_END #endif /* YOSYS_ENABLE_VERIFIC */ @@ -1789,6 +1836,7 @@ struct VerificPass : public Pass { if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU)) log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + verific_import_pending = true; goto check_error; } @@ -1797,6 +1845,7 @@ struct VerificPass : public Pass { for (argidx++; argidx < GetSize(args); argidx++) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87)) log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str()); + verific_import_pending = true; goto check_error; } @@ -1805,6 +1854,7 @@ struct VerificPass : public Pass { for (argidx++; argidx < GetSize(args); argidx++) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93)) log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str()); + verific_import_pending = true; goto check_error; } @@ -1813,6 +1863,7 @@ struct VerificPass : public Pass { for (argidx++; argidx < GetSize(args); argidx++) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K)) log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str()); + verific_import_pending = true; goto check_error; } @@ -1821,6 +1872,7 @@ struct VerificPass : public Pass { for (argidx++; argidx < GetSize(args); argidx++) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008)) log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str()); + verific_import_pending = true; goto check_error; } @@ -2031,6 +2083,7 @@ struct VerificPass : public Pass { veri_file::Reset(); vhdl_file::Reset(); Libset::Reset(); + verific_import_pending = false; goto check_error; } diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 86a743ea1..cbd9314db 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -25,6 +25,9 @@ YOSYS_NAMESPACE_BEGIN extern int verific_verbose; +extern bool verific_import_pending; +extern void verific_import(Design *design, std::string top = std::string()); + extern pool verific_sva_prims; struct VerificImporter; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index bfb8e7f95..e61851481 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -18,6 +18,7 @@ */ #include "kernel/yosys.h" +#include "frontends/verific/verific.h" #include #include #include @@ -421,6 +422,7 @@ struct HierarchyPass : public Pass { bool flag_simcheck = false; bool purge_lib = false; RTLIL::Module *top_mod = NULL; + std::string load_top_mod; std::vector libdirs; bool auto_top_mode = false; @@ -511,7 +513,7 @@ struct HierarchyPass : public Pass { top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL; } if (top_mod == NULL) - log_cmd_error("Module `%s' not found!\n", args[argidx].c_str()); + load_top_mod = args[argidx]; continue; } if (args[argidx] == "-auto-top") { @@ -522,6 +524,22 @@ struct HierarchyPass : public Pass { } extra_args(args, argidx, design, false); + if (!load_top_mod.empty()) { +#ifdef YOSYS_ENABLE_VERIFIC + if (verific_import_pending) { + verific_import(design, load_top_mod); + top_mod = design->module(RTLIL::escape_id(load_top_mod)); + } +#endif + if (top_mod == NULL) + log_cmd_error("Module `%s' not found!\n", load_top_mod.c_str()); + } else { +#ifdef YOSYS_ENABLE_VERIFIC + if (verific_import_pending) + verific_import(design); +#endif + } + if (generate_mode) { generate(design, generate_cells, generate_ports); return; From d412b17259ad7c2003dc14ec452a2a0a6fc3ba91 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 21 Jun 2018 16:56:55 +0200 Subject: [PATCH 108/184] Add simplified "read" command, enable extnets in implicit Verific import Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 84 ++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ab5c545a1..3c6566f62 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1641,6 +1641,10 @@ void verific_import(Design *design, std::string top) if (!verific_error_msg.empty()) log_error("%s\n", verific_error_msg.c_str()); + VerificExtNets worker; + for (auto nl : nl_todo) + worker.run(nl); + while (!nl_todo.empty()) { Netlist *nl = *nl_todo.begin(); if (nl_done.count(nl) == 0) { @@ -2101,5 +2105,85 @@ struct VerificPass : public Pass { #endif } VerificPass; +struct ReadPass : public Pass { + ReadPass() : Pass("read", "load HDL designs") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} ..\n"); + log("\n"); + log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n"); + log("is only available via Verific.)\n"); + log("\n"); + log("\n"); + log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} ..\n"); + log("\n"); + log("Load the specified VHDL files. (Requires Verific.)\n"); + log("\n"); + log("\n"); + log(" read -define [=]..\n"); + log("\n"); + log("Set global Verilog/SystemVerilog defines.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + if (args.size() < 2) + log_cmd_error("Missing mode parameter.\n"); + + if (args.size() < 3) + log_cmd_error("Missing file name parameter.\n"); + + if (args[1] == "-vlog95" || args[1] == "-vlog2k") { +#ifdef YOSYS_ENABLE_VERIFIC + args[0] = "verific"; +#else + args[0] = "read_verilog"; + args.erase(args.begin()+1, args.begin()+2); +#endif + Pass::call(design, args); + return; + } + + if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv") { +#ifdef YOSYS_ENABLE_VERIFIC + args[0] = "verific"; +#else + args[0] = "read_verilog"; + args[1] = "-sv"; +#endif + Pass::call(design, args); + return; + } + + if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl") { +#ifdef YOSYS_ENABLE_VERIFIC + args[0] = "verific"; +#else + log_cmd_error("This version of Yosys is built without Verific support.\n"); +#endif + Pass::call(design, args); + return; + } + + if (args[1] == "-define") { +#ifdef YOSYS_ENABLE_VERIFIC + args[0] = "verific"; + args[1] = "-vlog-define"; + Pass::call(design, args); +#endif + args[0] = "verilog_defines"; + args.erase(args.begin()+1, args.begin()+2); + for (int i = 1; i < GetSize(args); i++) + args[i] = "-D" + args[i]; + Pass::call(design, args); + return; + } + + log_cmd_error("Missing or unsupported mode parameter.\n"); + } +} ReadPass; + PRIVATE_NAMESPACE_END From 848c3c5c889945f64ddefc8fe45342a4338dc769 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 22 Jun 2018 20:40:22 +0200 Subject: [PATCH 109/184] Add YOSYS_NOVERIFIC env variable for temporarily disabling verific Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 62 +++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 22 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 3c6566f62..fb27810dd 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1669,6 +1669,16 @@ YOSYS_NAMESPACE_END PRIVATE_NAMESPACE_BEGIN +bool check_noverific_env() +{ + const char *e = getenv("YOSYS_NOVERIFIC"); + if (e == nullptr) + return false; + if (atoi(e) == 0) + return false; + return true; +} + struct VerificPass : public Pass { VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } virtual void help() @@ -1759,6 +1769,9 @@ struct VerificPass : public Pass { #ifdef YOSYS_ENABLE_VERIFIC virtual void execute(std::vector args, RTLIL::Design *design) { + if (check_noverific_env()) + log_cmd_error("This version of Yosys is built without Verific support.\n"); + log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n"); Message::SetConsoleOutput(0); @@ -2135,44 +2148,50 @@ struct ReadPass : public Pass { if (args.size() < 3) log_cmd_error("Missing file name parameter.\n"); - if (args[1] == "-vlog95" || args[1] == "-vlog2k") { #ifdef YOSYS_ENABLE_VERIFIC - args[0] = "verific"; + bool use_verific = !check_noverific_env(); #else - args[0] = "read_verilog"; - args.erase(args.begin()+1, args.begin()+2); + bool use_verific = false; #endif + + if (args[1] == "-vlog95" || args[1] == "-vlog2k") { + if (use_verific) { + args[0] = "verific"; + } else { + args[0] = "read_verilog"; + args.erase(args.begin()+1, args.begin()+2); + } Pass::call(design, args); return; } if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv") { -#ifdef YOSYS_ENABLE_VERIFIC - args[0] = "verific"; -#else - args[0] = "read_verilog"; - args[1] = "-sv"; -#endif + if (use_verific) { + args[0] = "verific"; + } else { + args[0] = "read_verilog"; + args[1] = "-sv"; + } Pass::call(design, args); return; } if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl") { -#ifdef YOSYS_ENABLE_VERIFIC - args[0] = "verific"; -#else - log_cmd_error("This version of Yosys is built without Verific support.\n"); -#endif - Pass::call(design, args); + if (use_verific) { + args[0] = "verific"; + Pass::call(design, args); + } else { + log_cmd_error("This version of Yosys is built without Verific support.\n"); + } return; } if (args[1] == "-define") { -#ifdef YOSYS_ENABLE_VERIFIC - args[0] = "verific"; - args[1] = "-vlog-define"; - Pass::call(design, args); -#endif + if (use_verific) { + args[0] = "verific"; + args[1] = "-vlog-define"; + Pass::call(design, args); + } args[0] = "verilog_defines"; args.erase(args.begin()+1, args.begin()+2); for (int i = 1; i < GetSize(args); i++) @@ -2186,4 +2205,3 @@ struct ReadPass : public Pass { } ReadPass; PRIVATE_NAMESPACE_END - From ee7164b87902313fe7a4af616891340b449db900 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Wed, 27 Jun 2018 16:26:36 -0400 Subject: [PATCH 110/184] Use msys2-provided pthreads instead of abc's. --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 11803ec0a..e8d7addf5 100644 --- a/Makefile +++ b/Makefile @@ -217,7 +217,7 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDLIBS := $(filter-out -lrt,$(LDLIBS)) ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" -ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=0 +ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)" EXE = .exe else ifneq ($(CONFIG),none) From 7e5801beedf63a713386433672429dbc607819c7 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Wed, 27 Jun 2018 16:33:34 -0400 Subject: [PATCH 111/184] Add support for 64-bit builds using msys2 environment. --- Makefile | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e8d7addf5..35759d559 100644 --- a/Makefile +++ b/Makefile @@ -5,6 +5,7 @@ CONFIG := clang # CONFIG := emcc # CONFIG := mxe # CONFIG := msys2 +# CONFIG := msys2-64 # features (the more the better) ENABLE_TCL := 1 @@ -220,8 +221,19 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)" EXE = .exe +else ifeq ($(CONFIG),msys2-64) +CXX = x86_64-w64-mingw32-g++ +LD = x86_64-w64-mingw32-g++ +CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR +CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) +LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s +LDLIBS := $(filter-out -lrt,$(LDLIBS)) +ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" +ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)" +EXE = .exe + else ifneq ($(CONFIG),none) -$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2) +$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2, msys2-64) endif ifeq ($(ENABLE_LIBYOSYS),1) @@ -676,6 +688,9 @@ config-mxe: clean config-msys2: clean echo 'CONFIG := msys2' > Makefile.conf +config-msys2-64: clean + echo 'CONFIG := msys2-64' > Makefile.conf + config-gprof: clean echo 'CONFIG := gcc' > Makefile.conf echo 'ENABLE_GPROF := 1' >> Makefile.conf From fe2ee833e154691ef61cc72833b86e02266039a2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 28 Jun 2018 16:57:03 +0200 Subject: [PATCH 112/184] Fix handling of signed memories Signed-off-by: Clifford Wolf --- frontends/ast/genrtlil.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 40cbbc2a3..d9f0039af 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1300,6 +1300,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); + if (!sign_hint) + is_signed = false; + return RTLIL::SigSpec(wire); } From 07e616900c2d6ddf021644f9687954d92ac8109a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 28 Jun 2018 23:43:38 +0200 Subject: [PATCH 113/184] Add "read -undef" Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fb27810dd..4fa74df3d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1715,6 +1715,11 @@ struct VerificPass : public Pass { log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n"); log("\n"); log("\n"); + log(" verific -vlog-undef ..\n"); + log("\n"); + log("Remove Verilog defines previously set with -vlog-define.\n"); + log("\n"); + log("\n"); log(" verific -import [options] ..\n"); log("\n"); log("Elaborate the design for the specified top modules, import to Yosys and\n"); @@ -1828,6 +1833,14 @@ struct VerificPass : public Pass { goto check_error; } + if (GetSize(args) > argidx && args[argidx] == "-vlog-undef") { + for (argidx++; argidx < GetSize(args); argidx++) { + string name = args[argidx]; + veri_file::UndefineMacro(name.c_str()); + } + goto check_error; + } + if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" || args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv")) { @@ -2139,6 +2152,11 @@ struct ReadPass : public Pass { log("\n"); log("Set global Verilog/SystemVerilog defines.\n"); log("\n"); + log("\n"); + log(" read -undef ..\n"); + log("\n"); + log("Unset global Verilog/SystemVerilog defines.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { @@ -2200,6 +2218,20 @@ struct ReadPass : public Pass { return; } + if (args[1] == "-undef") { + if (use_verific) { + args[0] = "verific"; + args[1] = "-vlog-undef"; + Pass::call(design, args); + } + args[0] = "verilog_defines"; + args.erase(args.begin()+1, args.begin()+2); + for (int i = 1; i < GetSize(args); i++) + args[i] = "-U" + args[i]; + Pass::call(design, args); + return; + } + log_cmd_error("Missing or unsupported mode parameter.\n"); } } ReadPass; From afedb2d03ee07738025ae77d73d280044c29ec2f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 28 Jun 2018 23:58:15 +0200 Subject: [PATCH 114/184] Add "read -sv -D" support Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 4fa74df3d..c9a071f70 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1693,6 +1693,9 @@ struct VerificPass : public Pass { log("Files passed to different calls to this command are treated as belonging to\n"); log("different compilation units.\n"); log("\n"); + log("Additional -D[=] options may be added after the option indicating\n"); + log("the language version (and before file names) to set additional verilog defines.\n"); + log("\n"); log("\n"); log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} ..\n"); log("\n"); @@ -1860,8 +1863,25 @@ struct VerificPass : public Pass { else log_abort(); - for (argidx++; argidx < GetSize(args); argidx++) - file_names.Insert(args[argidx].c_str()); + for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].substr(0, 2) == "-D"; argidx++) { + std::string name = args[argidx].substr(2); + if (args[argidx] == "-D") { + if (++argidx >= GetSize(args)) + break; + name = args[argidx]; + } + size_t equal = name.find('='); + if (equal != std::string::npos) { + string value = name.substr(equal+1); + name = name.substr(0, equal); + veri_file::DefineMacro(name.c_str(), value.c_str()); + } else { + veri_file::DefineMacro(name.c_str()); + } + } + + while (argidx < GetSize(args)) + file_names.Insert(args[argidx++].c_str()); if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU)) log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); @@ -2142,6 +2162,9 @@ struct ReadPass : public Pass { log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n"); log("is only available via Verific.)\n"); log("\n"); + log("Additional -D[=] options may be added after the option indicating\n"); + log("the language version (and before file names) to set additional verilog defines.\n"); + log("\n"); log("\n"); log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} ..\n"); log("\n"); From ebf0f003d3e8d219b396d4c6a3943e1ce54d2879 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 29 Jun 2018 10:02:27 +0200 Subject: [PATCH 115/184] Add "verific -formal" and "read -formal" Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c9a071f70..62a8028b8 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1695,8 +1695,13 @@ struct VerificPass : public Pass { log("\n"); log("Additional -D[=] options may be added after the option indicating\n"); log("the language version (and before file names) to set additional verilog defines.\n"); + log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n"); log("\n"); log("\n"); + log(" verific -formal ..\n"); + log("\n"); + log("Like -sv, but define FORMAL instead of SYNTHESIS.\n"); + log("\n"); log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} ..\n"); log("\n"); log("Load the specified VHDL files into Verific.\n"); @@ -1715,7 +1720,7 @@ struct VerificPass : public Pass { log("\n"); log(" verific -vlog-define [=]..\n"); log("\n"); - log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n"); + log("Add Verilog defines.\n"); log("\n"); log("\n"); log(" verific -vlog-undef ..\n"); @@ -1790,8 +1795,6 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("db_infer_wide_operators", 1); - veri_file::DefineCmdLineMacro("VERIFIC"); - veri_file::DefineCmdLineMacro("SYNTHESIS"); verific_verbose = 0; @@ -1845,7 +1848,7 @@ struct VerificPass : public Pass { } if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" || - args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv")) + args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal")) { Array file_names; unsigned verilog_mode; @@ -1858,11 +1861,14 @@ struct VerificPass : public Pass { verilog_mode = veri_file::SYSTEM_VERILOG_2005; else if (args[argidx] == "-sv2009") verilog_mode = veri_file::SYSTEM_VERILOG_2009; - else if (args[argidx] == "-sv2012" || args[argidx] == "-sv") + else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") verilog_mode = veri_file::SYSTEM_VERILOG; else log_abort(); + veri_file::DefineMacro("VERIFIC"); + veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS"); + for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].substr(0, 2) == "-D"; argidx++) { std::string name = args[argidx].substr(2); if (args[argidx] == "-D") { @@ -2157,7 +2163,7 @@ struct ReadPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} ..\n"); + log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} ..\n"); log("\n"); log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n"); log("is only available via Verific.)\n"); @@ -2206,11 +2212,13 @@ struct ReadPass : public Pass { return; } - if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv") { + if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv" || args[1] == "-formal") { if (use_verific) { args[0] = "verific"; } else { args[0] = "read_verilog"; + if (args[1] == "-formal") + args.insert(args.begin()+1, std::string()); args[1] = "-sv"; } Pass::call(design, args); From 0404cf61d5f230de70bc6e6e6bf907bf7b112e0d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 29 Jun 2018 19:21:04 +0200 Subject: [PATCH 116/184] Add verific support for eventually properties Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 110 ++++++++++++++++++++++++++++++-- 1 file changed, 105 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 4e440b4ca..9312fd6e6 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -980,7 +980,6 @@ struct VerificSvaImporter bool mode_assume = false; bool mode_cover = false; bool mode_trigger = false; - bool eventually = false; Instance *net_to_ast_driver(Net *n) { @@ -1487,6 +1486,69 @@ struct VerificSvaImporter fsm.getFirstAcceptReject(accept_p, reject_p); } + bool eventually_property(Net *&net, SigBit &trig) + { + if (clocking.cond_net != nullptr) + trig = importer->net_map_at(clocking.cond_net); + else + trig = State::S1; + + Instance *inst = net_to_ast_driver(net); + + if (inst->Type() == PRIM_SVA_S_EVENTUALLY || inst->Type() == PRIM_SVA_EVENTUALLY) + { + if (mode_cover || mode_trigger) + parser_error(inst); + + net = inst->GetInput(); + clocking.cond_net = nullptr; + + return true; + } + + if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION || + inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) + { + Net *antecedent_net = inst->GetInput1(); + Net *consequent_net = inst->GetInput2(); + + Instance *consequent_inst = net_to_ast_driver(consequent_net); + + if (consequent_inst->Type() != PRIM_SVA_S_EVENTUALLY && consequent_inst->Type() != PRIM_SVA_EVENTUALLY) { + return false; + } + + if (mode_cover || mode_trigger) + parser_error(consequent_inst); + + int node; + + log_dump(trig); + SvaFsm antecedent_fsm(clocking, trig); + node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net); + if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) { + int next_node = antecedent_fsm.createNode(); + antecedent_fsm.createEdge(node, next_node); + node = next_node; + } + antecedent_fsm.createLink(node, antecedent_fsm.acceptNode); + + trig = antecedent_fsm.getAccept(); + net = consequent_inst->GetInput(); + clocking.cond_net = nullptr; + + if (verific_verbose) { + log(" Eventually Antecedent FSM:\n"); + antecedent_fsm.dump(); + log_dump(trig); + } + + return true; + } + + return false; + } + void parse_property(Net *net, SigBit *accept_p, SigBit *reject_p) { Instance *inst = net_to_ast_driver(net); @@ -1620,10 +1682,48 @@ struct VerificSvaImporter } else { - if (mode_assert || mode_assume) { - parse_property(clocking.body_net, nullptr, &reject_bit); - } else { - parse_property(clocking.body_net, &accept_bit, nullptr); + Net *net = clocking.body_net; + SigBit trig; + + if (eventually_property(net, trig)) + { + SigBit sig_a, sig_en = trig; + parse_property(net, &sig_a, nullptr); + + log_dump(trig, sig_a, sig_en); + + // add final FF stage + + SigBit sig_a_q, sig_en_q; + + if (clocking.body_net == nullptr) { + sig_a_q = sig_a; + sig_en_q = sig_en; + } else { + sig_a_q = module->addWire(NEW_ID); + sig_en_q = module->addWire(NEW_ID); + clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0); + clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0); + } + + // generate fair/live cell + + RTLIL::Cell *c = nullptr; + + if (mode_assert) c = module->addLive(root_name, sig_a_q, sig_en_q); + if (mode_assume) c = module->addFair(root_name, sig_a_q, sig_en_q); + + importer->import_attributes(c->attributes, root); + + return; + } + else + { + if (mode_assert || mode_assume) { + parse_property(net, nullptr, &reject_bit); + } else { + parse_property(net, &accept_bit, nullptr); + } } } From 8b92ddb9d2635c30636b17ff3d24bc09a44b8551 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 29 Jun 2018 19:24:58 +0200 Subject: [PATCH 117/184] Fix verific eventually handling Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 9312fd6e6..8e985c3a6 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1488,13 +1488,16 @@ struct VerificSvaImporter bool eventually_property(Net *&net, SigBit &trig) { + Instance *inst = net_to_ast_driver(net); + + if (inst == nullptr) + return false; + if (clocking.cond_net != nullptr) trig = importer->net_map_at(clocking.cond_net); else trig = State::S1; - Instance *inst = net_to_ast_driver(net); - if (inst->Type() == PRIM_SVA_S_EVENTUALLY || inst->Type() == PRIM_SVA_EVENTUALLY) { if (mode_cover || mode_trigger) @@ -1523,7 +1526,6 @@ struct VerificSvaImporter int node; - log_dump(trig); SvaFsm antecedent_fsm(clocking, trig); node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net); if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) { @@ -1540,7 +1542,6 @@ struct VerificSvaImporter if (verific_verbose) { log(" Eventually Antecedent FSM:\n"); antecedent_fsm.dump(); - log_dump(trig); } return true; @@ -1690,8 +1691,6 @@ struct VerificSvaImporter SigBit sig_a, sig_en = trig; parse_property(net, &sig_a, nullptr); - log_dump(trig, sig_a, sig_en); - // add final FF stage SigBit sig_a_q, sig_en_q; From 0caa62802ccb3ee67e05c948a9e334504cae9cc4 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Fri, 6 Jul 2018 01:36:41 -0400 Subject: [PATCH 118/184] Gate POSIX-only signals and resource module to only run on POSIX Python implementations. --- backends/smt2/smtio.py | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index 1a8d2484c..3fc823e3e 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -17,7 +17,9 @@ # import sys, re, os, signal -import resource, subprocess +import subprocess +if os.name == "posix": + import resource from copy import deepcopy from select import select from time import time @@ -27,12 +29,13 @@ from threading import Thread # This is needed so that the recursive SMT2 S-expression parser # does not run out of stack frames when parsing large expressions -smtio_reclimit = 64 * 1024 -smtio_stacksize = 128 * 1024 * 1024 -if sys.getrecursionlimit() < smtio_reclimit: - sys.setrecursionlimit(smtio_reclimit) -if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize: - resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, -1)) +if os.name == "posix": + smtio_reclimit = 64 * 1024 + smtio_stacksize = 128 * 1024 * 1024 + if sys.getrecursionlimit() < smtio_reclimit: + sys.setrecursionlimit(smtio_reclimit) + if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize: + resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, -1)) # currently running solvers (so we can kill them) @@ -51,8 +54,9 @@ def force_shutdown(signum, frame): os.kill(p.pid, signal.SIGTERM) sys.exit(1) +if os.name == "posix": + signal.signal(signal.SIGHUP, force_shutdown) signal.signal(signal.SIGINT, force_shutdown) -signal.signal(signal.SIGHUP, force_shutdown) signal.signal(signal.SIGTERM, force_shutdown) def except_hook(exctype, value, traceback): @@ -1053,4 +1057,3 @@ class MkVcd: print("b0 %s" % self.nets[path][0], file=self.f) else: print("b1 %s" % self.nets[path][0], file=self.f) - From cd65eeb3b3a2410e6e42f35e8ab58be4276fd104 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 13:09:18 +0200 Subject: [PATCH 119/184] ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC Signed-off-by: David Shah --- techlibs/ice40/cells_sim.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 45a02111f..9f73aeb07 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -657,7 +657,12 @@ module ICESTORM_LC ( parameter [0:0] SET_NORESET = 0; parameter [0:0] ASYNC_SR = 0; - assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx; + parameter [0:0] CIN_CONST = 0; + parameter [0:0] CIN_SET = 0; + + wire mux_cin = CIN_CONST ? CIN_SET : CIN; + + assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx; wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0]; @@ -1226,4 +1231,3 @@ module SB_IO_OD ( endgenerate `endif endmodule - From b1b9e23f949410fe7c337491a5813f2741a5d9a1 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 13:27:24 +0200 Subject: [PATCH 120/184] ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7 Signed-off-by: David Shah --- techlibs/ecp5/cells_map.v | 86 +++++++++ techlibs/ecp5/cells_sim.v | 387 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 473 insertions(+) create mode 100644 techlibs/ecp5/cells_map.v create mode 100644 techlibs/ecp5/cells_sim.v diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v new file mode 100644 index 000000000..399697c14 --- /dev/null +++ b/techlibs/ecp5/cells_map.v @@ -0,0 +1,86 @@ +`ifndef NO_LUT +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(A[0]), .B(1'b0), .C(1'b0), .D(1'b0)); + end else + if (WIDTH == 2) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(A[0]), .B(A[1]), .C(1'b0), .D(1'b0)); + end else + if (WIDTH == 3) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(A[0]), .B(A[1]), .C(A[2]), .D(1'b0)); + end else + if (WIDTH == 4) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + `ifndef NO_PFUMUX + end else + if (WIDTH == 5) begin + wire f0, f1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + PFUMX mux5(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(Y)); + end else + if (WIDTH == 6) begin + wire f0, f1, f2, f3, g0, g1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1)); + L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y)); + end else + if (WIDTH == 7) begin + wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1)); + PFUMX mux52(.ALUT(f5), .BLUT(f4), .SD(A[4]), .Z(g2)); + PFUMX mux53(.ALUT(f7), .BLUT(f6), .SD(A[4]), .Z(g3)); + L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0)); + L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1)); + L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y)); + `endif + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule +`endif diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v new file mode 100644 index 000000000..54006218f --- /dev/null +++ b/techlibs/ecp5/cells_sim.v @@ -0,0 +1,387 @@ +// --------------------------------------- + +module LUT4(input A, B, C, D, output Z); + parameter [15:0] INIT = 16'h0000; + assign Z = INIT[{D, C, B, A}]; +endmodule + +// --------------------------------------- + +module L6MUX21 (input D0, D1, SD, output Z); + assign Z = SD ? D1 : D0; +endmodule + +// --------------------------------------- + +module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, COUT); + + parameter [15:0] INIT0 = 16'h0000; + parameter [15:0] INIT1 = 16'h0000; + parameter INJECT1_0 = "YES"; + parameter INJECT1_1 = "YES"; + + // First half + wire LUT4_0 = INIT0[{D0, C0, B0, A0}]; + wire LUT2_0 = INIT0[{2'b00, B0, A0}]; + + wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; + assign S0 = LUT4_0 ^ gated_cin_0; + + wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; + wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); + + // Second half + wire LUT4_1 = INIT1[{D1, C1, B1, A1}]; + wire LUT2_1 = INIT1[{2'b00, B1, A1}]; + + wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; + assign S1 = LUT4_1 ^ gated_cin_1; + + wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; + assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); + +endmodule + +// --------------------------------------- + +module TRELLIS_RAM16X2 ( + input DI0, DI1, + input WAD0, WAD1, WAD2, WAD3, + input WRE, WCK, + input RAD0, RAD1, RAD2, RAD3, + output DO0, DO1 +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter INITVAL_0 = 16'h0000; + parameter INITVAL_1 = 16'h0000; + + reg [1:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= {INITVAL_1[i], INITVAL_0[i]}; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + wire muxwre = (WREMUX == "1") ? 1'b1 : + (WREMUX == "0") ? 1'b0 : + (WREMUX == "INV") ? ~WRE : + WRE; + + always @(posedge muxwck) + if (muxwre) + mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0}; + + assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}]; +endmodule + +// --------------------------------------- + +module PFUMX (input ALUT, BLUT, C0, output Z); + assign Z = C0 ? ALUT : BLUT; +endmodule + +// --------------------------------------- + +module DPR16X4C ( + input [3:0] DI, + input WCK, WRE, + input [3:0] RAD, + input [3:0] WAD, + output [3:0] DO +); + // For legacy Lattice compatibility, INITIVAL is a hex + // string rather than a numeric parameter + parameter INITVAL = "0x0000000000000000"; + + function [63:0] convert_initval; + input [143:0] hex_initval; + reg done; + reg [63:0] temp; + reg [7:0] char; + integer i; + begin + done = 1'b0; + temp = 0; + for (i = 0; i < 16; i = i + 1) begin + if (!done) begin + char = hex_initval[8*i +: 8]; + if (char == "x") begin + done = 1'b1; + end else begin + if (char >= "0" && char <= "9") + temp[4*i +: 4] = char - "0"; + else if (char >= "A" && char <= "F") + temp[4*i +: 4] = 10 + char - "A"; + else if (char >= "a" && char <= "f") + temp[4*i +: 4] = 10 + char - "a"; + end + end + end + convert_initval = temp; + end + endfunction + + localparam conv_initval = convert_initval(INITVAL); + + reg [3:0] ram[0:15]; + integer i; + initial begin + for (i = 0; i < 15; i = i + 1) begin + ram[i] = conv_initval[4*i +: 4]; + end + end + + always @(posedge WCK) + if (WRE) + ram[WAD] <= DI; + + assign DO = ram[RAD]; + +endmodule + +// --------------------------------------- + +module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q); + parameter GSR = "ENABLED"; + parameter [127:0] CEMUX = "1"; + parameter CLKMUX = "CLK"; + parameter LSRMUX = "LSR"; + parameter SRMODE = "LSR_OVER_CE"; + parameter REGSET = "RESET"; + + wire muxce = (CEMUX == "1") ? 1'b1 : + (CEMUX == "0") ? 1'b0 : + (CEMUX == "INV") ? ~CE : + CE; + + wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; + wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; + + wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; + + initial Q = 1'b0; + + generate + if (SRMODE == "ASYNC") begin + always @(posedge muxclk, posedge muxlsr) + if (muxlsr) + Q <= srval; + else + Q <= DI; + end else begin + always @(posedge muxclk) + if (muxlsr) + Q <= srval; + else + Q <= DI; + end + endgenerate +endmodule + +// --------------------------------------- + +module OBZ(input I, T, output O); +assign O = T ? 1'bz : I; +endmodule + +// --------------------------------------- + +module IB(input I, output O); +assign O = I; +endmodule + +// --------------------------------------- + +module TRELLIS_IO( + inout B, + input I, + input T, + output O +); + parameter DIR = "INPUT"; + + generate + if (DIR == "INPUT") begin + assign B = 1'bz; + assign O = B; + end else if (DIR == "OUTPUT") begin + assign B = T ? 1'bz : I; + assign O = 1'bx; + end else if (DIR == "INOUT") begin + assign B = T ? 1'bz : I; + assign O = B; + end else begin + ERROR_UNKNOWN_IO_MODE error(); + end + endgenerate + +endmodule + +// --------------------------------------- + +module OB(input I, output O); +assign O = I; +endmodule + +// --------------------------------------- + +module BB(input I, T, output O, inout B); +assign B = T ? 1'bz : I; +assign O = B; +endmodule + +// --------------------------------------- + +module INV(input A, output Z); + assign Z = !A; +endmodule + +// --------------------------------------- + +module TRELLIS_SLICE( + input A0, B0, C0, D0, + input A1, B1, C1, D1, + input M0, M1, + input FCI, FXA, FXB, + + input CLK, LSR, CE, + input DI0, DI1, + + input WD0, WD1, + input WAD0, WAD1, WAD2, WAD3, + input WRE, WCK, + + output F0, Q0, + output F1, Q1, + output FCO, OFX0, OFX1, + + output WDO0, WDO1, WDO2, WDO3, + output WADO0, WADO1, WADO2, WADO3 +); + + parameter MODE = "LOGIC"; + parameter GSR = "ENABLED"; + parameter SRMODE = "LSR_OVER_CE"; + parameter [127:0] CEMUX = "1"; + parameter CLKMUX = "CLK"; + parameter LSRMUX = "LSR"; + parameter LUT0_INITVAL = 16'h0000; + parameter LUT1_INITVAL = 16'h0000; + parameter REG0_SD = "0"; + parameter REG1_SD = "0"; + parameter REG0_REGSET = "RESET"; + parameter REG1_REGSET = "RESET"; + parameter [127:0] CCU2_INJECT1_0 = "NO"; + parameter [127:0] CCU2_INJECT1_1 = "NO"; + parameter WREMUX = "WRE"; + + function [15:0] permute_initval; + input [15:0] initval; + integer i; + begin + for (i = 0; i < 16; i = i + 1) begin + permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i]; + end + end + endfunction + + generate + if (MODE == "LOGIC") begin + // LUTs + LUT4 #( + .INIT(LUT0_INITVAL) + ) lut4_0 ( + .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0) + ); + LUT4 #( + .INIT(LUT1_INITVAL) + ) lut4_1 ( + .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1) + ); + // LUT expansion muxes + PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0)); + L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + end else if (MODE == "CCU2") begin + CCU2C #( + .INIT0(LUT0_INITVAL), + .INIT1(LUT1_INITVAL), + .INJECT1_0(CCU2_INJECT1_0), + .INJECT1_1(CCU2_INJECT1_1) + ) ccu2c_i ( + .CIN(FCI), + .A0(A0), .B0(B0), .C0(C0), .D0(D0), + .A1(A1), .B1(B1), .C1(C1), .D1(D1), + .S0(F0), .S1(F1), + .COUT(FCO) + ); + end else if (MODE == "RAMW") begin + assign WDO0 = C1; + assign WDO1 = A1; + assign WDO2 = D1; + assign WDO3 = B1; + assign WADO0 = D0; + assign WADO1 = B0; + assign WADO2 = C0; + assign WADO3 = A0; + end else if (MODE == "DPRAM") begin + TRELLIS_RAM16X2 #( + .INITVAL_0(permute_initval(LUT0_INITVAL)), + .INITVAL_1(permute_initval(LUT1_INITVAL)), + .WREMUX(WREMUX) + ) ram_i ( + .DI0(WD0), .DI1(WD1), + .WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3), + .WRE(WRE), .WCK(WCK), + .RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0), + .DO0(F0), .DO1(F1) + ); + // TODO: confirm RAD and INITVAL ordering + // DPRAM mode contract? + always @(*) begin + assert(A0==A1); + assert(B0==B1); + assert(C0==C1); + assert(D0==D1); + end + end else begin + ERROR_UNKNOWN_SLICE_MODE error(); + end + endgenerate + + // FF input selection muxes + wire muxdi0 = (REG0_SD == "1") ? DI0 : M0; + wire muxdi1 = (REG1_SD == "1") ? DI1 : M1; + // Flipflops + TRELLIS_FF #( + .GSR(GSR), + .CEMUX(CEMUX), + .CLKMUX(CLKMUX), + .LSRMUX(LSRMUX), + .SRMODE(SRMODE), + .REGSET(REG0_REGSET) + ) ff_0 ( + .CLK(CLK), .LSR(LSR), .CE(CE), + .DI(muxdi0), + .Q(Q0) + ); + TRELLIS_FF #( + .GSR(GSR), + .CEMUX(CEMUX), + .CLKMUX(CLKMUX), + .LSRMUX(LSRMUX), + .SRMODE(SRMODE), + .REGSET(REG1_REGSET) + ) ff_1 ( + .CLK(CLK), .LSR(LSR), .CE(CE), + .DI(muxdi1), + .Q(Q1) + ); +endmodule + From 1def34f2a64603a3186dc50460fe964f1f197a43 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 14:08:42 +0200 Subject: [PATCH 121/184] ecp5: Adding DRAM map Signed-off-by: David Shah --- techlibs/ecp5/cells_sim.v | 37 ++++++++++++++++++++++++++++++++++++- techlibs/ecp5/dram.txt | 12 ++++++++++++ techlibs/ecp5/drams_map.v | 28 ++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 techlibs/ecp5/dram.txt create mode 100644 techlibs/ecp5/drams_map.v diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 54006218f..06e6133a7 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -52,7 +52,7 @@ module TRELLIS_RAM16X2 ( input RAD0, RAD1, RAD2, RAD3, output DO0, DO1 ); - parameter WCKMUX = "WCK"; + parameter WCKMUX = "WCK"; parameter WREMUX = "WRE"; parameter INITVAL_0 = 16'h0000; parameter INITVAL_1 = 16'h0000; @@ -87,6 +87,41 @@ endmodule // --------------------------------------- +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + + reg [3:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= INITVAL[4*i :+ 4]; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + wire muxwre = (WREMUX == "1") ? 1'b1 : + (WREMUX == "0") ? 1'b0 : + (WREMUX == "INV") ? ~WRE : + WRE; + + always @(posedge muxwck) + if (muxwre) + mem[WAD] <= DI; + + assign DO = mem[RAD]; +endmodule + +// --------------------------------------- + module DPR16X4C ( input [3:0] DI, input WCK, WRE, diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt new file mode 100644 index 000000000..a13111f0c --- /dev/null +++ b/techlibs/ecp5/dram.txt @@ -0,0 +1,12 @@ +bram $__TRELLIS_DPR16X4 + init 1 + abits 4 + dbits 4 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v new file mode 100644 index 000000000..3b3de831f --- /dev/null +++ b/techlibs/ecp5/drams_map.v @@ -0,0 +1,28 @@ +module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); + parameter [63:0] INIT = 64'bx; + parameter CLKPOL2 = 1; + input CLK1; + + input [3:0] A1ADDR; + output [3:0] A1DATA; + + input [3:0] B1ADDR; + input [3:0] B1DATA; + input B1EN; + + localparam WCKMUX = CLKPOL2 ? "WCK" : "INV"; + + TRELLIS_DPR16X4 #( + .INITVAL(INIT), + .WCKMUX(WCKMUX), + .WREMUX("WRE") + ) _TECHMAP_REPLACE_ ( + .RAD(A1ADDR), + .DO(A1DATA), + + .WAD(B1ADDR), + .DI(B1DATA), + .WCK(CLK1), + .WRE(B1EN) + ); +endmodule From eb8f3f7dc467156ffaec0ed1a471fe5e610709c7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 14:32:23 +0200 Subject: [PATCH 122/184] ecp5: Adding DFF maps Signed-off-by: David Shah --- techlibs/ecp5/cells_map.v | 29 +++++++++++++++++++++++++++++ techlibs/ecp5/cells_sim.v | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 399697c14..05874ec09 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -1,3 +1,32 @@ +module \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule +module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule + +module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule + `ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 06e6133a7..32aec4e93 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -199,7 +199,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q); wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; - initial Q = 1'b0; + initial Q = srval; generate if (SRMODE == "ASYNC") begin From c2d7be140a2b40ecb553f87437c6f958786030ad Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 14:52:25 +0200 Subject: [PATCH 123/184] ecp5: Adding basic synth_ecp5 based on synth_ice40 Signed-off-by: David Shah --- techlibs/ecp5/Makefile.inc | 7 + techlibs/ecp5/cells_map.v | 14 +- techlibs/ecp5/synth_ecp5.cc | 331 ++++++++++++++++++++++++++++++++++++ 3 files changed, 345 insertions(+), 7 deletions(-) create mode 100644 techlibs/ecp5/Makefile.inc create mode 100644 techlibs/ecp5/synth_ecp5.cc diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc new file mode 100644 index 000000000..e0900f8f4 --- /dev/null +++ b/techlibs/ecp5/Makefile.inc @@ -0,0 +1,7 @@ + +OBJS += techlibs/ecp5/synth_ecp5.o + +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt)) diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 05874ec09..6bce03755 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -59,7 +59,7 @@ module \$lut (A, Y); .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); - PFUMX mux5(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(Y)); + PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y)); end else if (WIDTH == 6) begin wire f0, f1, f2, f3, g0, g1; @@ -73,8 +73,8 @@ module \$lut (A, Y); LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); - PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0)); - PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1)); + PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1)); L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y)); end else if (WIDTH == 7) begin @@ -99,10 +99,10 @@ module \$lut (A, Y); LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); - PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0)); - PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1)); - PFUMX mux52(.ALUT(f5), .BLUT(f4), .SD(A[4]), .Z(g2)); - PFUMX mux53(.ALUT(f7), .BLUT(f6), .SD(A[4]), .Z(g3)); + PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1)); + PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2)); + PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3)); L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0)); L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1)); L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y)); diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc new file mode 100644 index 000000000..219496738 --- /dev/null +++ b/techlibs/ecp5/synth_ecp5.cc @@ -0,0 +1,331 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2018 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthEcp5Pass : public ScriptPass +{ + SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { } + + virtual void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_ecp5 [options]\n"); + log("\n"); + log("This command runs synthesis for ECP5 FPGAs.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -blif \n"); + log(" write the design to the specified BLIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -edif \n"); + log(" write the design to the specified EDIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log(" -noccu2\n"); + log(" do not use CCU2 cells in output netlist\n"); + log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); + log("\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); + log("\n"); + log(" -nomux\n"); + log(" do not use PFU muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -abc2\n"); + log(" run two passes of 'abc' for slightly improved logic density\n"); + log("\n"); + log(" -vpr\n"); + log(" generate an output netlist (and BLIF file) suitable for VPR\n"); + log(" (this feature is experimental and incomplete)\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, blif_file, edif_file, json_file; + bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr; + + virtual void clear_flags() YS_OVERRIDE + { + top_opt = "-auto-top"; + blif_file = ""; + edif_file = ""; + json_file = ""; + noccu2 = false; + nodffe = false; + nobram = false; + nodram = false; + nomux = false; + flatten = true; + retime = false; + abc2 = false; + vpr = false; + } + + virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-blif" && argidx+1 < args.size()) { + blif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx+1 < args.size()) { + edif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-flatten") { + flatten = true; + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-retime") { + retime = true; + continue; + } + if (args[argidx] == "-noccu2") { + noccu2 = true; + continue; + } + if (args[argidx] == "-nodffe") { + nodffe = true; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-nodram") { + nodram = true; + continue; + } + if (args[argidx] == "-abc2") { + abc2 = true; + continue; + } + if (args[argidx] == "-vpr") { + vpr = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!design->full_selection()) + log_cmd_error("This comannd only operates on fully selected designs!\n"); + + log_header(design, "Executing SYNTH_ECP5 pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + virtual void script() YS_OVERRIDE + { + if (check_label("begin")) + { + run("read_verilog -lib +/ecp5/cells_sim.v"); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + } + + if (flatten && check_label("flatten", "(unless -noflatten)")) + { + run("proc"); + run("flatten"); + run("tribuf -logic"); + run("deminout"); + } + + if (check_label("coarse")) + { + run("synth -run coarse"); + } + + if (!nobram && check_label("bram", "(skip if -nobram)")) + { + //TODO +#if 0 + run("memory_bram -rules +/ecp5/brams.txt"); + run("techmap -map +/ecp5/brams_map.v"); +#endif + } + + if (!nodram && check_label("dram", "(skip if -nodram)")) + { + run("memory_bram -rules +/ecp5/dram.txt"); + run("techmap -map +/ecp5/drams_map.v"); + } + + if (check_label("fine")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine"); + //TODO +#if 0 + if (nocarry) + run("techmap"); + else + run("techmap -map +/techmap.v -map +/ecp5/arith_map.v"); +#else + run("techmap"); +#endif + if (retime || help_mode) + run("abc -dff", "(only if -retime)"); + } + + if (check_label("map_ffs")) + { + run("dffsr2dff"); + if (!nodffe) + run("dff2dffe -direct-match $_DFF_*"); + run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); + run("opt_expr -mux_undef"); + run("simplemap"); + // TODO +#if 0 + run("ecp5_ffinit"); + run("ecp5_ffssr"); +#endif + } + + if (check_label("map_luts")) + { + if (abc2 || help_mode) { + run("abc", " (only if -abc2)"); + } + //TODO +#if 0 + run("techmap -map +/ecp5/latches_map.v"); +#endif + if (nomux) + run("abc -lut 4"); + else + run("abc -lut 4:7"); + run("clean"); + } + + if (check_label("map_cells")) + { + if (vpr) + run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); + else + run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)"); + + run("clean"); + } + + if (check_label("check")) + { + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + } + + if (check_label("blif")) + { + if (!blif_file.empty() || help_mode) { + if (vpr || help_mode) { + run(stringf("opt_clean -purge"), + " (vpr mode)"); + run(stringf("write_blif -attr -cname -conn -param %s", + help_mode ? "" : blif_file.c_str()), + " (vpr mode)"); + } + if (!vpr) + run(stringf("write_blif -gates -attr -param %s", + help_mode ? "" : blif_file.c_str()), + " (non-vpr mode)"); + } + } + + if (check_label("edif")) + { + if (!edif_file.empty() || help_mode) + run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + } + } +} SynthEcp5Pass; + +PRIVATE_NAMESPACE_END From 11c916840d127d7e32fd9689f1c86cdc847352e0 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 15:46:12 +0200 Subject: [PATCH 124/184] ecp5: Initial arith_map implementation Signed-off-by: David Shah --- techlibs/ecp5/Makefile.inc | 1 + techlibs/ecp5/arith_map.v | 78 +++++++++++++++++++++++++++++++++++++ techlibs/ecp5/synth_ecp5.cc | 7 +--- 3 files changed, 80 insertions(+), 6 deletions(-) create mode 100644 techlibs/ecp5/arith_map.v diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index e0900f8f4..9d3247347 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -5,3 +5,4 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v new file mode 100644 index 000000000..3c2b86deb --- /dev/null +++ b/techlibs/ecp5/arith_map.v @@ -0,0 +1,78 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$alu" *) +module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + function integer round_up2; + input integer N; + begin + round_up2 = ((N / 2) + 1) * 2; + end + endfunction + + localparam Y_WIDTH2 = round_up2(Y_WIDTH); + + wire [Y_WIDTH2-1:0] AA = A_buf; + wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH2-1:0] C = {CO, CI}; + wire [Y_WIDTH2-1:0] FCO; + + genvar i; + generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice + CCU2C #( + .INIT0(16'b0110011010101010), + .INIT1(16'b0110011010101010), + .INJECT1_0(1'b0), + .INJECT1_1(1'b0) + ) ccu2c_i ( + .CIN(C[i]), + .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1), + .A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1), + .S0(F0), .S1(F1), + .COUT(FCO[i]) + ); + + assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); + if (i < Y_WIDTH) + assign CO[i+1] = FCO[i]; + + end endgenerate + + assign X = AA ^ BB; +endmodule diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 219496738..86d2027de 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -236,15 +236,10 @@ struct SynthEcp5Pass : public ScriptPass run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); - //TODO -#if 0 - if (nocarry) + if (noccu2) run("techmap"); else run("techmap -map +/techmap.v -map +/ecp5/arith_map.v"); -#else - run("techmap"); -#endif if (retime || help_mode) run("abc -dff", "(only if -retime)"); } From b0fea67cc66ceac64e2cb71874c36cde21aa34df Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 15:49:59 +0200 Subject: [PATCH 125/184] ecp5: Fixing arith_map Signed-off-by: David Shah --- techlibs/ecp5/arith_map.v | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index 3c2b86deb..cf21ee80e 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -51,7 +51,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH2-1:0] AA = A_buf; wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH2-1:0] C = {CO, CI}; - wire [Y_WIDTH2-1:0] FCO; + wire [Y_WIDTH2-1:0] FCO, Y1; genvar i; generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice @@ -64,14 +64,15 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); .CIN(C[i]), .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1), .A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1), - .S0(F0), .S1(F1), + .S0(Y[i]), .S1(Y1[i]), .COUT(FCO[i]) ); assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); - if (i < Y_WIDTH) + if (i < Y_WIDTH) begin assign CO[i+1] = FCO[i]; - + assign Y[i+1] = Y1[i]; + end end endgenerate assign X = AA ^ BB; From 4a60bc83ab47b76632b38fcaec4cefffa152f507 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 16:14:08 +0200 Subject: [PATCH 126/184] ecp5: Cells and mappings fixes Signed-off-by: David Shah --- techlibs/ecp5/arith_map.v | 6 +++--- techlibs/ecp5/cells_sim.v | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index cf21ee80e..05d44b9b4 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -58,12 +58,12 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); CCU2C #( .INIT0(16'b0110011010101010), .INIT1(16'b0110011010101010), - .INJECT1_0(1'b0), - .INJECT1_1(1'b0) + .INJECT1_0("NO"), + .INJECT1_1("NO") ) ccu2c_i ( .CIN(C[i]), .A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1), - .A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1), + .A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1), .S0(Y[i]), .S1(Y1[i]), .COUT(FCO[i]) ); diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 32aec4e93..6c53a78eb 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -103,7 +103,7 @@ module TRELLIS_DPR16X4 ( integer i; initial begin for (i = 0; i < 16; i = i + 1) - mem[i] <= INITVAL[4*i :+ 4]; + mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]}; end wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; @@ -197,7 +197,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q); wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; - wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; + localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0; initial Q = srval; From 241429abac67de34b073db46550b1c2b4a42d425 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 13 Jul 2018 16:25:52 +0200 Subject: [PATCH 127/184] ecp5: Add DRAM match rule Signed-off-by: David Shah --- techlibs/ecp5/dram.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt index a13111f0c..b3252fa9a 100644 --- a/techlibs/ecp5/dram.txt +++ b/techlibs/ecp5/dram.txt @@ -10,3 +10,7 @@ bram $__TRELLIS_DPR16X4 clocks 0 1 clkpol 0 2 endbram + +match $__TRELLIS_DPR16X4 + make_outreg +endmatch From 459d3679134d4e30d9b4bfbc7007368d229c9e9f Mon Sep 17 00:00:00 2001 From: David Shah Date: Sat, 14 Jul 2018 15:54:30 +0200 Subject: [PATCH 128/184] ecp5: Adding synchronous set/reset support Signed-off-by: David Shah --- passes/techmap/Makefile.inc | 2 +- passes/techmap/dff2dffe.cc | 14 +++- passes/techmap/dff2dffs.cc | 142 ++++++++++++++++++++++++++++++++++++ techlibs/ecp5/cells_map.v | 52 +++++++++---- techlibs/ecp5/synth_ecp5.cc | 5 +- 5 files changed, 194 insertions(+), 21 deletions(-) create mode 100644 passes/techmap/dff2dffs.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 140a9f892..4faa0ab00 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -35,6 +35,7 @@ OBJS += passes/techmap/insbuf.o OBJS += passes/techmap/attrmvcp.o OBJS += passes/techmap/attrmap.o OBJS += passes/techmap/zinit.o +OBJS += passes/techmap/dff2dffs.o endif GENFILES += passes/techmap/techmap.inc @@ -57,4 +58,3 @@ yosys-filterlib$(EXE): passes/techmap/filterlib.o $(Q) mkdir -p $(dir $@) $(P) $(LD) -o yosys-filterlib$(EXE) $(LDFLAGS) $^ $(LDLIBS) endif - diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 1b8920bb7..4d515f174 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -279,8 +279,9 @@ struct Dff2dffePass : public Pass { log(" -direct-match \n"); log(" like -direct for all DFF cell types matching the expression.\n"); log(" this will use $__DFFE_* as matching the\n"); - log(" internal gate type $_DFF_*_, except for $_DFF_[NP]_, which is\n"); - log(" converted to $_DFFE_[NP]_.\n"); + log(" internal gate type $_DFF_*_, and $__DFFSE_* for those matching\n"); + log(" $_DFFS_*_, except for $_DFF_[NP]_, which is converted to \n"); + log(" $_DFFE_[NP]_.\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) @@ -315,6 +316,15 @@ struct Dff2dffePass : public Pass { if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict["$_DFF_PN1_"] = "$__DFFE_PN1"; if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict["$_DFF_PP0_"] = "$__DFFE_PP0"; if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict["$_DFF_PP1_"] = "$__DFFE_PP1"; + + if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict["$__DFFS_NN0_"] = "$__DFFSE_NN0"; + if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict["$__DFFS_NN1_"] = "$__DFFSE_NN1"; + if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict["$__DFFS_NP0_"] = "$__DFFSE_NP0"; + if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict["$__DFFS_NP1_"] = "$__DFFSE_NP1"; + if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict["$__DFFS_PN0_"] = "$__DFFSE_PN0"; + if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict["$__DFFS_PN1_"] = "$__DFFSE_PN1"; + if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict["$__DFFS_PP0_"] = "$__DFFSE_PP0"; + if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict["$__DFFS_PP1_"] = "$__DFFSE_PP1"; if (!found_match) log_cmd_error("No cell types matched pattern '%s'.\n", pattern); continue; diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc new file mode 100644 index 000000000..0bfbdc965 --- /dev/null +++ b/passes/techmap/dff2dffs.cc @@ -0,0 +1,142 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2018 David Shah + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct Dff2dffsPass : public Pass { + Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { } + virtual void help() + { + log("\n"); + log(" dff2dffs [options] [selection]\n"); + log("\n"); + log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n"); + log("dff2dffe for SR over CE priority.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // if (args[argidx] == "-singleton") { + // singleton_mode = true; + // continue; + // } + break; + } + extra_args(args, argidx, design); + + pool dff_types; + dff_types.insert("$_DFF_N_"); + dff_types.insert("$_DFF_P_"); + + for (auto module : design->selected_modules()) + { + log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module)); + + SigMap sigmap(module); + dict sr_muxes; + vector ff_cells; + + for (auto cell : module->selected_cells()) + { + if (dff_types.count(cell->type)) { + ff_cells.push_back(cell); + continue; + } + + if (cell->type != "$_MUX_") + continue; + + SigBit bit_a = sigmap(cell->getPort("\\A")); + SigBit bit_b = sigmap(cell->getPort("\\B")); + + if (bit_a.wire == nullptr || bit_b.wire == nullptr) + sr_muxes[sigmap(cell->getPort("\\Y"))] = cell; + } + + for (auto cell : ff_cells) + { + SigSpec sig_d = cell->getPort("\\D"); + + if (GetSize(sig_d) < 1) + continue; + + SigBit bit_d = sigmap(sig_d[0]); + + if (sr_muxes.count(bit_d) == 0) + continue; + + Cell *mux_cell = sr_muxes.at(bit_d); + SigBit bit_a = sigmap(mux_cell->getPort("\\A")); + SigBit bit_b = sigmap(mux_cell->getPort("\\B")); + SigBit bit_s = sigmap(mux_cell->getPort("\\S")); + + log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell), + log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type)); + + SigBit sr_val, sr_sig; + bool invert_sr; + sr_sig = bit_s; + if (bit_a.wire == nullptr) { + bit_d = bit_b; + sr_val = bit_a; + invert_sr = true; + } else { + log_assert(bit_b.wire == nullptr); + bit_d = bit_a; + sr_val = bit_b; + invert_sr = false; + } + + if (sr_val == State::S1) { + if (cell->type == "$_DFF_N_") { + if (invert_sr) cell->type = "$__DFFS_NN1_"; + else cell->type = "$__DFFS_NP1_"; + } else { + log_assert(cell->type == "$_DFF_P_"); + if (invert_sr) cell->type = "$__DFFS_PN1_"; + else cell->type = "$__DFFS_PP1_"; + } + } else { + if (cell->type == "$_DFF_N_") { + if (invert_sr) cell->type = "$__DFFS_NN0_"; + else cell->type = "$__DFFS_NP0_"; + } else { + log_assert(cell->type == "$_DFF_P_"); + if (invert_sr) cell->type = "$__DFFS_PN0_"; + else cell->type = "$__DFFS_PP0_"; + } + } + cell->setPort("\\R", sr_sig); + cell->setPort("\\D", bit_d); + } + } + } +} Dff2dffsPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v index 6bce03755..48162a4dc 100644 --- a/techlibs/ecp5/cells_map.v +++ b/techlibs/ecp5/cells_map.v @@ -7,25 +7,45 @@ module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .C module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule -module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule -module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule + +module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule +module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule `ifndef NO_LUT module \$lut (A, Y); diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 86d2027de..b54bf4204 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -247,15 +247,16 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("map_ffs")) { run("dffsr2dff"); + run("dff2dffs"); + run("opt_clean"); if (!nodffe) - run("dff2dffe -direct-match $_DFF_*"); + run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); // TODO #if 0 run("ecp5_ffinit"); - run("ecp5_ffssr"); #endif } From b2c62ff8efb9650ac3eefab4e7756b7ba303962e Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 16 Jul 2018 14:33:13 +0200 Subject: [PATCH 129/184] ecp5: ECP5 synthesis fixes Signed-off-by: David Shah --- techlibs/ecp5/arith_map.v | 4 ++-- techlibs/ecp5/cells_sim.v | 39 ++++++++++++++++++++++++------------- techlibs/ecp5/synth_ecp5.cc | 4 ++++ 3 files changed, 32 insertions(+), 15 deletions(-) diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v index 05d44b9b4..1094c5f8a 100644 --- a/techlibs/ecp5/arith_map.v +++ b/techlibs/ecp5/arith_map.v @@ -42,7 +42,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); function integer round_up2; input integer N; begin - round_up2 = ((N / 2) + 1) * 2; + round_up2 = ((N + 1) / 2) * 2; end endfunction @@ -69,7 +69,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); ); assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); - if (i < Y_WIDTH) begin + if (i+1 < Y_WIDTH) begin assign CO[i+1] = FCO[i]; assign Y[i+1] = Y1[i]; end diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 6c53a78eb..1755da24b 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -67,10 +67,15 @@ module TRELLIS_RAM16X2 ( wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; - wire muxwre = (WREMUX == "1") ? 1'b1 : - (WREMUX == "0") ? 1'b0 : - (WREMUX == "INV") ? ~WRE : - WRE; + reg muxwre; + always @(*) + case (WREMUX) + "1": muxwre = 1'b1; + "0": muxwre = 1'b0; + "INV": muxwre = ~WRE; + default: muxwre = WRE; + endcase + always @(posedge muxwck) if (muxwre) @@ -108,10 +113,14 @@ module TRELLIS_DPR16X4 ( wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; - wire muxwre = (WREMUX == "1") ? 1'b1 : - (WREMUX == "0") ? 1'b0 : - (WREMUX == "INV") ? ~WRE : - WRE; + reg muxwre; + always @(*) + case (WREMUX) + "1": muxwre = 1'b1; + "0": muxwre = 1'b0; + "INV": muxwre = ~WRE; + default: muxwre = WRE; + endcase always @(posedge muxwck) if (muxwre) @@ -167,7 +176,7 @@ module DPR16X4C ( integer i; initial begin for (i = 0; i < 15; i = i + 1) begin - ram[i] = conv_initval[4*i +: 4]; + ram[i] <= conv_initval[4*i +: 4]; end end @@ -189,10 +198,14 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q); parameter SRMODE = "LSR_OVER_CE"; parameter REGSET = "RESET"; - wire muxce = (CEMUX == "1") ? 1'b1 : - (CEMUX == "0") ? 1'b0 : - (CEMUX == "INV") ? ~CE : - CE; + reg muxce; + always @(*) + case (CEMUX) + "1": muxce = 1'b1; + "0": muxce = 1'b0; + "INV": muxce = ~CE; + default: muxce = CE; + endcase wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index b54bf4204..76051d1a2 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -172,6 +172,10 @@ struct SynthEcp5Pass : public ScriptPass nodram = true; continue; } + if (args[argidx] == "-nomux") { + nomux = true; + continue; + } if (args[argidx] == "-abc2") { abc2 = true; continue; From e9ef077266652b4a76773287199a0b7f18b94a3d Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 16 Jul 2018 15:20:34 +0200 Subject: [PATCH 130/184] ecp5: Fixing 'X' issues with LUT simulation models Signed-off-by: David Shah --- techlibs/ecp5/cells_sim.v | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 1755da24b..cf1446a52 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -1,8 +1,11 @@ // --------------------------------------- module LUT4(input A, B, C, D, output Z); - parameter [15:0] INIT = 16'h0000; - assign Z = INIT[{D, C, B, A}]; + parameter [15:0] INIT = 16'h0000; + wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0]; + wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0]; + assign Z = A ? s1[1] : s1[0]; endmodule // --------------------------------------- @@ -22,8 +25,9 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, parameter INJECT1_1 = "YES"; // First half - wire LUT4_0 = INIT0[{D0, C0, B0, A0}]; - wire LUT2_0 = INIT0[{2'b00, B0, A0}]; + wire LUT4_0, LUT2_0; + LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); + LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; assign S0 = LUT4_0 ^ gated_cin_0; @@ -32,8 +36,9 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1, wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); // Second half - wire LUT4_1 = INIT1[{D1, C1, B1, A1}]; - wire LUT2_1 = INIT1[{2'b00, B1, A1}]; + wire LUT4_1, LUT2_1; + LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); + LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; assign S1 = LUT4_1 ^ gated_cin_1; @@ -190,6 +195,14 @@ endmodule // --------------------------------------- +module LUT2(input A, B, output Z); + parameter [3:0] INIT = 4'h0; + wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; + assign Z = A ? s1[1] : s1[0]; +endmodule + +// --------------------------------------- + module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q); parameter GSR = "ENABLED"; parameter [127:0] CEMUX = "1"; From f39b897545c0f9b4d02c77cc7b6cd2a3bfc6082f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 16 Jul 2018 15:32:26 +0200 Subject: [PATCH 131/184] Add "read -incdir" Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 62a8028b8..ab752b96d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2186,6 +2186,11 @@ struct ReadPass : public Pass { log("\n"); log("Unset global Verilog/SystemVerilog defines.\n"); log("\n"); + log("\n"); + log(" read -incdir \n"); + log("\n"); + log("Add directory to global Verilog/SystemVerilog include directories.\n"); + log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { @@ -2263,6 +2268,20 @@ struct ReadPass : public Pass { return; } + if (args[1] == "-incdir") { + if (use_verific) { + args[0] = "verific"; + args[1] = "-vlog-incdir"; + Pass::call(design, args); + } + args[0] = "verilog_defaults"; + args[1] = "-add"; + for (int i = 1; i < GetSize(args); i++) + args[i] = "-I" + args[i]; + Pass::call(design, args); + return; + } + log_cmd_error("Missing or unsupported mode parameter.\n"); } } ReadPass; From 3a3558acce25807d6ce75280cc3f43aeb52974df Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 16 Jul 2018 15:56:12 +0200 Subject: [PATCH 132/184] ecp5: Fixing miscellaneous sim model issues Signed-off-by: David Shah --- techlibs/ecp5/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index cf1446a52..1700694e8 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q); always @(posedge muxclk, posedge muxlsr) if (muxlsr) Q <= srval; - else + else if (muxce) Q <= DI; end else begin always @(posedge muxclk) if (muxlsr) Q <= srval; - else + else if (muxce) Q <= DI; end endgenerate From f897af626dc8f84c79dc9274a5a5fa868018480f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 16 Jul 2018 16:48:09 +0200 Subject: [PATCH 133/184] Fix "read -incdir" Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ab752b96d..54b682082 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2276,7 +2276,7 @@ struct ReadPass : public Pass { } args[0] = "verilog_defaults"; args[1] = "-add"; - for (int i = 1; i < GetSize(args); i++) + for (int i = 2; i < GetSize(args); i++) args[i] = "-I" + args[i]; Pass::call(design, args); return; From 5041ed2f7df1e932eed6bc4ad38fb0f0973700af Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 16 Jul 2018 18:46:06 +0200 Subject: [PATCH 134/184] Fix verific -vlog-incdir and -vlog-libdir handling Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 54b682082..8937cdde8 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -65,6 +65,8 @@ int verific_verbose; bool verific_import_pending; string verific_error_msg; +vector verific_incdirs, verific_libdirs; + void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args) { string message_prefix = stringf("VERIFIC-%s [%s] ", @@ -1658,6 +1660,8 @@ void verific_import(Design *design, std::string top) veri_file::Reset(); vhdl_file::Reset(); Libset::Reset(); + verific_incdirs.clear(); + verific_libdirs.clear(); verific_import_pending = false; if (!verific_error_msg.empty()) @@ -1814,13 +1818,13 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") { for (argidx++; argidx < GetSize(args); argidx++) - veri_file::AddIncludeDir(args[argidx].c_str()); + verific_incdirs.push_back(args[argidx]); goto check_error; } if (GetSize(args) > argidx && args[argidx] == "-vlog-libdir") { for (argidx++; argidx < GetSize(args); argidx++) - veri_file::AddYDir(args[argidx].c_str()); + verific_libdirs.push_back(args[argidx]); goto check_error; } @@ -1886,6 +1890,11 @@ struct VerificPass : public Pass { } } + for (auto &dir : verific_incdirs) + veri_file::AddIncludeDir(dir.c_str()); + for (auto &dir : verific_libdirs) + veri_file::AddYDir(dir.c_str()); + while (argidx < GetSize(args)) file_names.Insert(args[argidx++].c_str()); @@ -2139,6 +2148,8 @@ struct VerificPass : public Pass { veri_file::Reset(); vhdl_file::Reset(); Libset::Reset(); + verific_incdirs.clear(); + verific_libdirs.clear(); verific_import_pending = false; goto check_error; } From 65234d4b24edd1ec8ec5d41df2d56d76fa41dcc5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 17 Jul 2018 12:43:30 +0200 Subject: [PATCH 135/184] Fix handling of eventually properties in verific importer Signed-off-by: Clifford Wolf --- frontends/verific/verificsva.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 8e985c3a6..85b842186 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1517,9 +1517,11 @@ struct VerificSvaImporter Instance *consequent_inst = net_to_ast_driver(consequent_net); - if (consequent_inst->Type() != PRIM_SVA_S_EVENTUALLY && consequent_inst->Type() != PRIM_SVA_EVENTUALLY) { + if (consequent_inst == nullptr) + return false; + + if (consequent_inst->Type() != PRIM_SVA_S_EVENTUALLY && consequent_inst->Type() != PRIM_SVA_EVENTUALLY) return false; - } if (mode_cover || mode_trigger) parser_error(consequent_inst); From 87aef8f0cc9ee63fc8fe5eb26e6ceb73aa83b5c9 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 19 Jul 2018 15:31:12 +0200 Subject: [PATCH 136/184] Add async2sync pass Signed-off-by: Clifford Wolf --- passes/sat/Makefile.inc | 1 + passes/sat/async2sync.cc | 147 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+) create mode 100644 passes/sat/async2sync.cc diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc index 4fcce2fad..8ab0280c0 100644 --- a/passes/sat/Makefile.inc +++ b/passes/sat/Makefile.inc @@ -7,4 +7,5 @@ OBJS += passes/sat/miter.o OBJS += passes/sat/expose.o OBJS += passes/sat/assertpmux.o OBJS += passes/sat/clk2fflogic.o +OBJS += passes/sat/async2sync.o diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc new file mode 100644 index 000000000..85933acc2 --- /dev/null +++ b/passes/sat/async2sync.cc @@ -0,0 +1,147 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct Async2syncPass : public Pass { + Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" async2sync [options] [selection]\n"); + log("\n"); + log("This command replaces async FF inputs with sync circuits emulating the same\n"); + log("behavior for when the async signals are actually synchronized to the clock.\n"); + log("\n"); + log("This pass assumes negative hold time for the async FF inputs. For example when\n"); + log("a reset deasserts with the clock edge, then the FF output will still drive the\n"); + log("reset value in the next cycle regardless of the data-in value at the time of\n"); + log("the clock edge.\n"); + log("\n"); + log("Currently only $adff cells are supported by this pass.\n"); + log("\n"); + } + virtual void execute(std::vector args, RTLIL::Design *design) + { + // bool flag_noinit = false; + + log_header(design, "Executing ASYNC2SYNC pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // if (args[argidx] == "-noinit") { + // flag_noinit = true; + // continue; + // } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + SigMap sigmap(module); + dict initbits; + pool del_initbits; + + for (auto wire : module->wires()) + if (wire->attributes.count("\\init") > 0) + { + Const initval = wire->attributes.at("\\init"); + SigSpec initsig = sigmap(wire); + + for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) + if (initval[i] == State::S0 || initval[i] == State::S1) + initbits[initsig[i]] = initval[i]; + } + + for (auto cell : vector(module->selected_cells())) + { + if (cell->type.in("$adff")) + { + // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool(); + bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool(); + Const arst_val = cell->parameters["\\ARST_VALUE"]; + + SigSpec sig_clk = cell->getPort("\\CLK"); + SigSpec sig_arst = cell->getPort("\\ARST"); + SigSpec sig_d = cell->getPort("\\D"); + SigSpec sig_q = cell->getPort("\\Q"); + + log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n", + log_id(module), log_id(cell), log_id(cell->type), + log_signal(sig_arst), log_signal(sig_d), log_signal(sig_q)); + + Const init_val; + for (int i = 0; i < GetSize(sig_q); i++) { + SigBit bit = sigmap(sig_q[i]); + init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx); + del_initbits.insert(bit); + } + + Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d)); + Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); + new_q->attributes["\\init"] = init_val; + + if (arst_pol) { + module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d); + module->addMux(NEW_ID, new_q, arst_val, sig_arst, sig_q); + } else { + module->addMux(NEW_ID, arst_val, sig_d, sig_arst, new_d); + module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q); + } + + cell->setPort("\\D", new_d); + cell->setPort("\\Q", new_q); + cell->unsetPort("\\ARST"); + cell->unsetParam("\\ARST_POLARITY"); + cell->unsetParam("\\ARST_VALUE"); + cell->type = "$dff"; + continue; + } + } + + for (auto wire : module->wires()) + if (wire->attributes.count("\\init") > 0) + { + bool delete_initattr = true; + Const initval = wire->attributes.at("\\init"); + SigSpec initsig = sigmap(wire); + + for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) + if (del_initbits.count(initsig[i]) > 0) + initval[i] = State::Sx; + else if (initval[i] != State::Sx) + delete_initattr = false; + + if (delete_initattr) + wire->attributes.erase("\\init"); + else + wire->attributes.at("\\init") = initval; + } + } + } +} Async2syncPass; + +PRIVATE_NAMESPACE_END From 1a60126a3468c525ac31de930dfb139b70512a34 Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Thu, 19 Jul 2018 09:40:20 -0700 Subject: [PATCH 137/184] Provide source-location logging. o Provide log_file_warning() and log_file_error() that prefix the log message with :: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil. --- frontends/ast/genrtlil.cc | 5 +-- kernel/log.cc | 86 +++++++++++++++++++-------------------- kernel/log.h | 5 +++ 3 files changed, 48 insertions(+), 48 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d9f0039af..b8208fa80 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -958,9 +958,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->name = str; if (flag_autowire) - log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str()); else - log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { if (id2ast->children[0]->type != AST_CONSTANT) @@ -1563,4 +1563,3 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict> get_coverage_data() #endif YOSYS_NAMESPACE_END - diff --git a/kernel/log.h b/kernel/log.h index a2aacfd4d..0b4905c3a 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -73,8 +73,13 @@ YS_NORETURN void logv_error(const char *format, va_list ap) YS_ATTRIBUTE(noretur void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3)); void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); + +// Log with filename to report a problem in a source file. +void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); + void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); +void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4), noreturn); YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn); void log_spacer(); From b5ea598ef6cec535378c8cbb53170ccd1e5855ca Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Fri, 20 Jul 2018 08:11:20 -0700 Subject: [PATCH 138/184] Use log_file_warning(), log_file_error() functions. Wherever we can report a source-level location. --- frontends/ast/genrtlil.cc | 32 +++---- frontends/ast/simplify.cc | 121 +++++++++++++------------- frontends/verilog/verilog_frontend.cc | 8 +- 3 files changed, 79 insertions(+), 82 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index b8208fa80..e611ddcb1 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -238,7 +238,7 @@ struct AST_INTERNAL::ProcessGenerator if (found_anyedge_syncs) { if (found_global_syncs) - log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum); + log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n"); log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum); log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n"); log("use of @* instead of @(...) for better match of synthesis and simulation.\n"); @@ -253,12 +253,12 @@ struct AST_INTERNAL::ProcessGenerator continue; found_clocked_sync = true; if (found_global_syncs || found_anyedge_syncs) - log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum); + log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n"); RTLIL::SyncRule *syncrule = new RTLIL::SyncRule; syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn; syncrule->signal = child->children[0]->genRTLIL(); if (GetSize(syncrule->signal) != 1) - log_error("Found posedge/negedge event on a signal that is not 1 bit wide at %s:%d!\n", always->filename.c_str(), always->linenum); + log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n"); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); proc->syncs.push_back(syncrule); } @@ -549,12 +549,12 @@ struct AST_INTERNAL::ProcessGenerator break; case AST_WIRE: - log_error("Found wire declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum); + log_file_error(ast->filename, ast->linenum, "Found wire declaration in block without label!\n"); break; case AST_PARAMETER: case AST_LOCALPARAM: - log_error("Found parameter declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum); + log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n"); break; case AST_NONE: @@ -602,7 +602,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (id_ast == NULL && current_scope.count(str)) id_ast = current_scope.at(str); if (!id_ast) - log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str()); if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) { if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; @@ -612,7 +612,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (id_ast->children[0]->type == AST_CONSTANT) this_width = id_ast->children[0]->bits.size(); else - log_error("Failed to detect width for parameter %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str()); if (children.size() != 0) range = children[0]; } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) { @@ -624,7 +624,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun // log("---\n"); // id_ast->dumpAst(NULL, "decl> "); // dumpAst(NULL, "ref> "); - log_error("Failed to detect width of signal access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str()); } } else { this_width = id_ast->range_left - id_ast->range_right + 1; @@ -635,10 +635,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun this_width = 32; } else if (id_ast->type == AST_MEMORY) { if (!id_ast->children[0]->range_valid) - log_error("Failed to detect width of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str()); this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1; } else - log_error("Failed to detect width for identifier %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str()); if (range) { if (range->children.size() == 1) this_width = 1; @@ -665,7 +665,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_TO_BITS: while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { } if (children[0]->type != AST_CONSTANT) - log_error("Left operand of tobits expression is not constant at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sign_hint); width_hint = max(width_hint, children[0]->bitsAsConst().as_int()); break; @@ -693,7 +693,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_REPLICATE: while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } if (children[0]->type != AST_CONSTANT) - log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint); width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint); sign_hint = false; @@ -767,7 +767,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (!id2ast->is_signed) sign_hint = false; if (!id2ast->children[0]->range_valid) - log_error("Failed to detect width of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str()); this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1; width_hint = max(width_hint, this_width); break; @@ -1083,7 +1083,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genRTLIL(); if (!left.is_fully_const()) - log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n"); int count = left.as_int(); RTLIL::SigSpec sig; for (int i = 0; i < count; i++) @@ -1322,7 +1322,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int num_words = 1; if (type == AST_MEMINIT) { if (children[2]->type != AST_CONSTANT) - log_error("Memory init with non-constant word count at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Memory init with non-constant word count!\n"); num_words = int(children[2]->asInt(false)); cell->parameters["\\WORDS"] = RTLIL::Const(num_words); } @@ -1514,7 +1514,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (attributes.count("\\reg")) { auto &attr = attributes.at("\\reg"); if (attr->type != AST_CONSTANT) - log_error("Attribute `reg' with non-constant value at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n"); cell->attributes["\\reg"] = attr->asAttrConst(); } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index a16fdfeeb..81bd3cd7e 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -177,13 +177,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" || str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) { - log_warning("Ignoring call to system %s %s at %s:%d.\n", type == AST_FCALL ? "function" : "task", str.c_str(), filename.c_str(), linenum); + log_file_warning(filename, linenum, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str()); delete_children(); str = std::string(); } if ((type == AST_TCALL) && (str == "$display" || str == "$write") && (!current_always || current_always->type != AST_INITIAL)) { - log_warning("System task `%s' outside initial block is unsupported at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_warning(filename, linenum, "System task `%s' outside initial block is unsupported.\n", str.c_str()); delete_children(); str = std::string(); } @@ -202,7 +202,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *node_string = children[0]; while (node_string->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_string->type != AST_CONSTANT) - log_error("Failed to evaluate system task `%s' with non-constant 1st argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str()); std::string sformat = node_string->bitsAsConst().decode_string(); // Other arguments are placeholders. Process the string as we go through it @@ -215,7 +215,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { // If there's no next character, that's a problem if (i+1 >= sformat.length()) - log_error("System task `%s' called with `%%' at end of string at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "System task `%s' called with `%%' at end of string.\n", str.c_str()); char cformat = sformat[++i]; @@ -245,7 +245,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, node_arg = children[next_arg++]; while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_arg->type != AST_CONSTANT) - log_error("Failed to evaluate system task `%s' with non-constant argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str()); break; case 'm': @@ -253,7 +253,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, break; default: - log_error("System task `%s' called with invalid/unsupported format specifier at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "System task `%s' called with invalid/unsupported format specifier.\n", str.c_str()); break; } @@ -374,7 +374,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, continue; wires_are_incompatible: if (stage > 1) - log_error("Incompatible re-declaration of wire %s at %s:%d.\n", node->str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Incompatible re-declaration of wire %s.\n", node->str.c_str()); continue; } this_wire_scope[node->str] = node; @@ -402,7 +402,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_ALWAYS || type == AST_INITIAL) { if (current_always != nullptr) - log_error("Invalid nesting of always blocks and/or initializations at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Invalid nesting of always blocks and/or initializations.\n"); current_always = this; current_always_clocked = false; @@ -451,7 +451,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, true) == true) did_something = true; if (!children[1]->range_valid) - log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Non-constant width range on parameter decl.\n"); width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1); } break; @@ -695,7 +695,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_DEFPARAM && !children.empty()) { if (children[0]->type != AST_IDENTIFIER) - log_error("Module name in defparam at %s:%d contains non-constant expressions!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Module name in defparam contains non-constant expressions!\n"); string modname, paramname = children[0]->str; @@ -712,7 +712,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (pos == std::string::npos) - log_error("Can't find object for defparam `%s` at %s:%d!\n", RTLIL::unescape_id(paramname).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str()); paramname = "\\" + paramname.substr(pos+1); @@ -732,7 +732,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_PREFIX) { if (children[0]->type != AST_CONSTANT) { // dumpAst(NULL, "> "); - log_error("Index in generate block prefix syntax at %s:%d is not constant!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Index in generate block prefix syntax is not constant!\n"); } if (children[1]->type == AST_PREFIX) children[1]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param); @@ -748,9 +748,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // evaluate TO_BITS nodes if (type == AST_TO_BITS) { if (children[0]->type != AST_CONSTANT) - log_error("Left operand of to_bits expression is not constant at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Left operand of to_bits expression is not constant!\n"); if (children[1]->type != AST_CONSTANT) - log_error("Right operand of to_bits expression is not constant at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Right operand of to_bits expression is not constant!\n"); RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed); newNode = mkconst_bits(new_value.bits, children[1]->is_signed); goto apply_newNode; @@ -814,7 +814,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, multirange_dimensions.clear(); for (auto range : children[1]->children) { if (!range->range_valid) - log_error("Non-constant range on memory decl at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Non-constant range on memory decl.\n"); multirange_dimensions.push_back(min(range->range_left, range->range_right)); multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1); total_size *= multirange_dimensions.back(); @@ -832,7 +832,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++) { if (GetSize(children[0]->children) < i) - log_error("Insufficient number of array indices for %s at %s:%d.\n", log_id(str), filename.c_str(), linenum); + log_file_error(filename, linenum, "Insufficient number of array indices for %s.\n", log_id(str)); AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone(); @@ -861,7 +861,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_PARAMETER || type == AST_LOCALPARAM) { if (children.size() > 1 && children[1]->type == AST_RANGE) { if (!children[1]->range_valid) - log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Non-constant width range on parameter decl.\n"); int width = std::abs(children[1]->range_left - children[1]->range_right) + 1; if (children[0]->type == AST_REALVALUE) { RTLIL::Const constvalue = children[0]->realAsConst(width); @@ -924,7 +924,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_IDENTIFIER && children.size() == 2 && children[0]->type == AST_RANGE && children[1]->type == AST_RANGE && !in_lvalue) { if (id2ast == NULL || id2ast->type != AST_MEMORY || children[0]->children.size() != 1) - log_error("Invalid bit-select on memory access at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Invalid bit-select on memory access!\n"); int mem_width, mem_size, addr_bits; id2ast->meminfo(mem_width, mem_size, addr_bits); @@ -973,10 +973,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (type == AST_WHILE) - log_error("While loops are only allowed in constant functions at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "While loops are only allowed in constant functions!\n"); if (type == AST_REPEAT) - log_error("Repeat loops are only allowed in constant functions at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Repeat loops are only allowed in constant functions!\n"); // unroll for loops and generate-for blocks if ((type == AST_GENFOR || type == AST_FOR) && children.size() != 0) @@ -991,31 +991,31 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, body_ast = body_ast->children.at(0); if (init_ast->type != AST_ASSIGN_EQ) - log_error("Unsupported 1st expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Unsupported 1st expression of generate for-loop!\n"); if (next_ast->type != AST_ASSIGN_EQ) - log_error("Unsupported 3rd expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Unsupported 3rd expression of generate for-loop!\n"); if (type == AST_GENFOR) { if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_GENVAR) - log_error("Left hand side of 1st expression of generate for-loop at %s:%d is not a gen var!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Left hand side of 1st expression of generate for-loop is not a gen var!\n"); if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_GENVAR) - log_error("Left hand side of 3rd expression of generate for-loop at %s:%d is not a gen var!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Left hand side of 3rd expression of generate for-loop is not a gen var!\n"); } else { if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_WIRE) - log_error("Left hand side of 1st expression of generate for-loop at %s:%d is not a register!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Left hand side of 1st expression of generate for-loop is not a register!\n"); if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_WIRE) - log_error("Left hand side of 3rd expression of generate for-loop at %s:%d is not a register!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Left hand side of 3rd expression of generate for-loop is not a register!\n"); } if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast) - log_error("Incompatible left-hand sides in 1st and 3rd expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Incompatible left-hand sides in 1st and 3rd expression of generate for-loop!\n"); // eval 1st expression AstNode *varbuf = init_ast->children[1]->clone(); while (varbuf->simplify(true, false, false, stage, 32, true, false)) { } if (varbuf->type != AST_CONSTANT) - log_error("Right hand side of 1st expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Right hand side of 1st expression of generate for-loop is not constant!\n"); varbuf = new AstNode(AST_LOCALPARAM, varbuf); varbuf->str = init_ast->children[0]->str; @@ -1037,7 +1037,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (buf->type != AST_CONSTANT) - log_error("2nd expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "2nd expression of generate for-loop is not constant!\n"); if (buf->integer == 0) { delete buf; @@ -1078,7 +1078,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (buf->simplify(true, false, false, stage, 32, true, false)) { } if (buf->type != AST_CONSTANT) - log_error("Right hand side of 3rd expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Right hand side of 3rd expression of generate for-loop is not constant!\n"); delete varbuf->children[0]; varbuf->children[0] = buf; @@ -1144,7 +1144,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_error("Condition for generate if at %s:%d is not constant!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Condition for generate if is not constant!\n"); } if (buf->asBool() != 0) { delete buf; @@ -1185,7 +1185,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_error("Condition for generate case at %s:%d is not constant!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Condition for generate case is not constant!\n"); } bool ref_signed = buf->is_signed; @@ -1219,7 +1219,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_error("Expression in generate case at %s:%d is not constant!\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Expression in generate case is not constant!\n"); } bool is_selected = RTLIL::const_eq(ref_value, buf->bitsAsConst(), ref_signed && buf->is_signed, ref_signed && buf->is_signed, 1).as_bool(); @@ -1260,7 +1260,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_CELLARRAY) { if (!children.at(0)->range_valid) - log_error("Non-constant array range on cell array at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Non-constant array range on cell array.\n"); newNode = new AstNode(AST_GENBLOCK); int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1; @@ -1271,7 +1271,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, newNode->children.push_back(new_cell); new_cell->str += stringf("[%d]", idx); if (new_cell->type == AST_PRIMITIVE) { - log_error("Cell arrays of primitives are currently not supported at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Cell arrays of primitives are currently not supported.\n"); } else { log_assert(new_cell->children.at(0)->type == AST_CELLTYPE); new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str()); @@ -1645,7 +1645,7 @@ skip_dynamic_range_lvalue_expansion:; while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), @@ -1749,7 +1749,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *buf = children[1]->clone(); while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (buf->type != AST_CONSTANT) - log_error("Failed to evaluate system function `%s' with non-constant value at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); num_steps = buf->asInt(true); delete buf; @@ -1846,7 +1846,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *buf = children[0]->clone(); while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (buf->type != AST_CONSTANT) - log_error("Failed to evaluate system function `%s' with non-constant value at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); RTLIL::Const arg_value = buf->bitsAsConst(); if (arg_value.as_bool()) @@ -1893,7 +1893,7 @@ skip_dynamic_range_lvalue_expansion:; if (id_ast == NULL && current_scope.count(buf->str)) id_ast = current_scope.at(buf->str); if (!id_ast) - log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", buf->str.c_str()); if (id_ast->type == AST_MEMORY) { // We got here only if the argument is a memory // Otherwise $size() and $bits() return the expression width @@ -1901,15 +1901,15 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$bits") { if (mem_range->type == AST_RANGE) { if (!mem_range->range_valid) - log_error("Failed to detect width of memory access `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", buf->str.c_str()); mem_depth = mem_range->range_left - mem_range->range_right + 1; } else - log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); } else { // $size() if (mem_range->type == AST_RANGE) { if (!mem_range->range_valid) - log_error("Failed to detect width of memory access `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", buf->str.c_str()); int dims; if (id_ast->multirange_dimensions.empty()) dims = 1; @@ -1920,9 +1920,9 @@ skip_dynamic_range_lvalue_expansion:; else if (dim <= dims) { width_hint = id_ast->multirange_dimensions[2*dim-1]; } else if ((dim > dims+1) || (dim < 0)) - log_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d at %s:%d!\n", dim, buf->str.c_str(), dims+1, filename.c_str(), linenum); + log_file_error(filename, linenum, "Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, buf->str.c_str(), dims+1); } else - log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); } } } @@ -2018,14 +2018,14 @@ skip_dynamic_range_lvalue_expansion:; for (int i = 2; i < GetSize(dpi_decl->children); i++) { if (i-2 >= GetSize(children)) - log_error("Insufficient number of arguments in DPI function call at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Insufficient number of arguments in DPI function call.\n"); argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str)); args.push_back(children.at(i-2)->clone()); while (args.back()->simplify(true, false, false, stage, -1, false, true)) { } if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE) - log_error("Failed to evaluate DPI function with non-constant argument at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate DPI function with non-constant argument.\n"); } newNode = dpi_call(rtype, fname, argtypes, args); @@ -2037,7 +2037,7 @@ skip_dynamic_range_lvalue_expansion:; } if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION) - log_error("Can't resolve function name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Can't resolve function name `%s'.\n", str.c_str()); } if (type == AST_TCALL) @@ -2045,9 +2045,9 @@ skip_dynamic_range_lvalue_expansion:; if (str == "$finish" || str == "$stop") { if (!current_always || current_always->type != AST_INITIAL) - log_error("System task `%s' outside initial block is unsupported at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "System task `%s' outside initial block is unsupported.\n", str.c_str()); - log_error("System task `%s' executed at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "System task `%s' executed.\n", str.c_str()); } if (str == "\\$readmemh" || str == "\\$readmemb") @@ -2059,12 +2059,12 @@ skip_dynamic_range_lvalue_expansion:; AstNode *node_filename = children[0]->clone(); while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_filename->type != AST_CONSTANT) - log_error("Failed to evaluate system function `%s' with non-constant 1st argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); AstNode *node_memory = children[1]->clone(); while (node_memory->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY) - log_error("Failed to evaluate system function `%s' with non-memory 2nd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str()); int start_addr = -1, finish_addr = -1; @@ -2072,7 +2072,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *node_addr = children[2]->clone(); while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_addr->type != AST_CONSTANT) - log_error("Failed to evaluate system function `%s' with non-constant 3rd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str()); start_addr = int(node_addr->asInt(false)); } @@ -2080,7 +2080,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *node_addr = children[3]->clone(); while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (node_addr->type != AST_CONSTANT) - log_error("Failed to evaluate system function `%s' with non-constant 4th argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str()); finish_addr = int(node_addr->asInt(false)); } @@ -2106,7 +2106,7 @@ skip_dynamic_range_lvalue_expansion:; } if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK) - log_error("Can't resolve task name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Can't resolve task name `%s'.\n", str.c_str()); } AstNode *decl = current_scope[str]; @@ -2134,9 +2134,9 @@ skip_dynamic_range_lvalue_expansion:; } if (in_param) - log_error("Non-constant function call in constant expression at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Non-constant function call in constant expression.\n"); if (require_const_eval) - log_error("Function %s can only be called with constant arguments at %s:%d.\n", str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Function %s can only be called with constant arguments.\n", str.c_str()); } size_t arg_count = 0; @@ -2253,7 +2253,7 @@ skip_dynamic_range_lvalue_expansion:; goto tcall_incompatible_wires; } else { tcall_incompatible_wires: - log_error("Incompatible re-declaration of wire %s at %s:%d.\n", child->str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Incompatible re-declaration of wire %s.\n", child->str.c_str()); } } } @@ -2641,7 +2641,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m yosys_input_files.insert(mem_filename); if (f.fail()) - log_error("Can not open file `%s` for %s at %s:%d.\n", mem_filename.c_str(), str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str()); log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid); int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right; @@ -2687,7 +2687,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m char *endptr; cursor = strtol(nptr, &endptr, 16); if (!*nptr || *endptr) - log_error("Can not parse address `%s` for %s at %s:%d.\n", nptr, str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Can not parse address `%s` for %s.\n", nptr, str.c_str()); continue; } @@ -2943,7 +2943,7 @@ bool AstNode::mem2reg_check(pool &mem2reg_set) return false; if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1) - log_error("Invalid array access at %s:%d.\n", filename.c_str(), linenum); + log_file_error(filename, linenum, "Invalid array access.\n"); return true; } @@ -3446,4 +3446,3 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) } YOSYS_NAMESPACE_END - diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 505c94619..be925fea2 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -42,7 +42,7 @@ static std::list> verilog_defaults_stack; static void error_on_dpi_function(AST::AstNode *node) { if (node->type == AST::AST_DPI_FUNCTION) - log_error("Found DPI function %s at %s:%d.\n", node->str.c_str(), node->filename.c_str(), node->linenum); + log_file_error(node->filename, node->linenum, "Found DPI function %s.\n", node->str.c_str()); for (auto child : node->children) error_on_dpi_function(child); } @@ -519,13 +519,11 @@ void frontend_verilog_yyerror(char const *fmt, ...) va_list ap; char buffer[1024]; char *p = buffer; - p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ", - YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); va_start(ap, fmt); p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap); va_end(ap); p += snprintf(p, buffer + sizeof(buffer) - p, "\n"); - YOSYS_NAMESPACE_PREFIX log_error("%s", buffer); + YOSYS_NAMESPACE_PREFIX log_file_error(YOSYS_NAMESPACE_PREFIX AST::current_filename, frontend_verilog_yyget_lineno(), + "%s", buffer); exit(1); } - From 68b5d0c3b11588946982939c00fd6febe198e13f Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Fri, 20 Jul 2018 09:37:44 -0700 Subject: [PATCH 139/184] Convert more log_error() to log_file_error() where possible. Mostly statements that span over multiple lines and haven't been caught with the previous conversion. --- frontends/ast/ast.cc | 13 ++- frontends/ast/genrtlil.cc | 140 ++++++++++++++++----------------- frontends/ast/simplify.cc | 107 +++++++++++++------------ frontends/verilog/const2ast.cc | 8 +- 4 files changed, 131 insertions(+), 137 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 999202b47..54ce6a05d 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -171,8 +171,8 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id) AstNode *attr = attributes.at(id); if (attr->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - id.c_str(), attr->filename.c_str(), attr->linenum); + log_file_error(attr->filename, attr->linenum, "Attribute `%s' with non-constant value!\n", + id.c_str()); return attr->integer != 0; } @@ -955,8 +955,8 @@ static AstModule* process_module(AstNode *ast, bool defer) for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), ast->filename.c_str(), ast->linenum); + log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); current_module->attributes[attr.first] = attr.second->asAttrConst(); } for (size_t i = 0; i < ast->children.size(); i++) { @@ -1044,8 +1044,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (design->has((*it)->str)) { RTLIL::Module *existing_mod = design->module((*it)->str); if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { - log_error("Re-definition of module `%s' at %s:%d!\n", - (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", + (*it)->str.c_str()); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s:%d.\n", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); @@ -1197,4 +1197,3 @@ void AST::use_internal_line_num() } YOSYS_NAMESPACE_END - diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index e611ddcb1..0f7e910f3 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -55,8 +55,8 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi if (gen_attributes) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), that->filename.c_str(), that->linenum); + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -89,8 +89,8 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s if (that != NULL) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), that->filename.c_str(), that->linenum); + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -117,8 +117,8 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), that->filename.c_str(), that->linenum); + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -152,8 +152,8 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), that->filename.c_str(), that->linenum); + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -207,8 +207,8 @@ struct AST_INTERNAL::ProcessGenerator proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++); for (auto &attr : always->attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), always->filename.c_str(), always->linenum); + log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); proc->attributes[attr.first] = attr.second->asAttrConst(); } current_module->processes[proc->name] = proc; @@ -480,8 +480,8 @@ struct AST_INTERNAL::ProcessGenerator for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), ast->filename.c_str(), ast->linenum); + log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); sw->attributes[attr.first] = attr.second->asAttrConst(); } @@ -648,8 +648,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", + str.c_str()); this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; delete left_at_zero_ast; delete right_at_zero_ast; @@ -777,8 +777,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (GetSize(children) == 1) { while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } if (children[0]->type != AST_CONSTANT) - log_error("System function %s called with non-const argument at %s:%d!\n", - RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s called with non-const argument!\n", + RTLIL::unescape_id(str).c_str()); width_hint = max(width_hint, int(children[0]->asInt(true))); } break; @@ -799,8 +799,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun default: for (auto f : log_files) current_ast->dumpAst(f, "verilog-ast> "); - log_error("Don't know how to detect sign and width for %s node at %s:%d!\n", - type2str(type).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", + type2str(type).c_str()); } if (*found_real) @@ -863,11 +863,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // create an RTLIL::Wire for an AST_WIRE node case AST_WIRE: { if (current_module->wires_.count(str) != 0) - log_error("Re-definition of signal `%s' at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", + str.c_str()); if (!range_valid) - log_error("Signal `%s' with non-constant width at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", + str.c_str()); log_assert(range_left >= range_right || (range_left == -1 && range_right == 0)); @@ -881,8 +881,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); wire->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -891,16 +891,16 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // create an RTLIL::Memory for an AST_MEMORY node case AST_MEMORY: { if (current_module->memories.count(str) != 0) - log_error("Re-definition of memory `%s' at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", + str.c_str()); log_assert(children.size() >= 2); log_assert(children[0]->type == AST_RANGE); log_assert(children[1]->type == AST_RANGE); if (!children[0]->range_valid || !children[1]->range_valid) - log_error("Memory `%s' with non-constant width or size at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", + str.c_str()); RTLIL::Memory *memory = new RTLIL::Memory; memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); @@ -917,8 +917,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); memory->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -937,8 +937,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_REALVALUE: { RTLIL::SigSpec sig = realAsConst(width_hint); - log_warning("converting real value %e to binary %s at %s:%d.\n", - realvalue, log_signal(sig), filename.c_str(), linenum); + log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", + realvalue, log_signal(sig)); return sig; } @@ -964,19 +964,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { if (id2ast->children[0]->type != AST_CONSTANT) - log_error("Parameter %s does not evaluate to constant value at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", + str.c_str()); chunk = RTLIL::Const(id2ast->children[0]->bits); goto use_const_chunk; } else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE && id2ast->type != AST_MEMORY) || current_module->wires_.count(str) == 0) - log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", + str.c_str()); if (id2ast->type == AST_MEMORY) - log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", + str.c_str()); wire = current_module->wires_[str]; chunk.wire = wire; @@ -994,8 +994,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", + str.c_str()); int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : children[0]->children[0]->clone()); @@ -1023,11 +1023,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width); if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) { if (chunk.width == 1) - log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n", - str.c_str(), filename.c_str(), linenum); + log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n", + str.c_str()); else - log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n", - str.c_str(), filename.c_str(), linenum, chunk.width); + log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting all %d result bits to undef.\n", + str.c_str(), chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); } else { if (chunk.width + chunk.offset > source_width) { @@ -1040,11 +1040,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.offset += add_undef_bits_lsb; } if (add_undef_bits_lsb) - log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n", - str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb); + log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d LSB bits to undef.\n", + str.c_str(), add_undef_bits_lsb); if (add_undef_bits_msb) - log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n", - str.c_str(), filename.c_str(), linenum, add_undef_bits_msb); + log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d MSB bits to undef.\n", + str.c_str(), add_undef_bits_msb); } } } @@ -1379,8 +1379,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -1401,10 +1401,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) new_left.append(left[i]); new_right.append(right[i]); } - log_warning("Ignoring assignment to constant bits at %s:%d:\n" - " old assignment: %s = %s\n new assignment: %s = %s.\n", - filename.c_str(), linenum, log_signal(left), log_signal(right), - log_signal(new_left), log_signal(new_right)); + log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n" + " old assignment: %s = %s\n new assignment: %s = %s.\n", + log_signal(left), log_signal(right), + log_signal(new_left), log_signal(new_right)); left = new_left; right = new_right; } @@ -1418,8 +1418,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int port_counter = 0, para_counter = 0; if (current_module->count_id(str) != 0) - log_error("Re-definition of cell `%s' at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str()); RTLIL::Cell *cell = current_module->addCell(str, ""); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); @@ -1435,16 +1434,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (child->type == AST_PARASET) { IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str; if (child->children[0]->type == AST_REALVALUE) { - log_warning("Replacing floating point parameter %s.%s = %f with string at %s:%d.\n", - log_id(cell), log_id(paraname), child->children[0]->realvalue, - filename.c_str(), linenum); + log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n", + log_id(cell), log_id(paraname), child->children[0]->realvalue); auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue)); strnode->cloneInto(child->children[0]); delete strnode; } if (child->children[0]->type != AST_CONSTANT) - log_error("Parameter %s.%s with non-constant value at %s:%d!\n", - log_id(cell), log_id(paraname), filename.c_str(), linenum); + log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n", + log_id(cell), log_id(paraname)); cell->parameters[paraname] = child->children[0]->asParaConst(); continue; } @@ -1465,8 +1463,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_error("Attribute `%s' with non-constant value at %s:%d!\n", - attr.first.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", + attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -1493,19 +1491,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = width_hint; if (GetSize(children) > 1) - log_error("System function %s got %d arguments, expected 1 or 0 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), GetSize(children), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n", + RTLIL::unescape_id(str).c_str(), GetSize(children)); if (GetSize(children) == 1) { if (children[0]->type != AST_CONSTANT) - log_error("System function %s called with non-const argument at %s:%d!\n", - RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s called with non-const argument!\n", + RTLIL::unescape_id(str).c_str()); width = children[0]->asInt(true); } if (width <= 0) - log_error("Failed to detect width of %s at %s:%d!\n", - RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to detect width of %s!\n", + RTLIL::unescape_id(str).c_str()); Cell *cell = current_module->addCell(myid, str.substr(1)); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); @@ -1532,8 +1530,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto f : log_files) current_ast->dumpAst(f, "verilog-ast> "); type_name = type2str(type); - log_error("Don't know how to generate RTLIL code for %s node at %s:%d!\n", - type_name.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", + type_name.c_str()); } return RTLIL::SigSpec(); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 81bd3cd7e..be53e8527 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -195,8 +195,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { int nargs = GetSize(children); if (nargs < 1) - log_error("System task `%s' got %d arguments, expected >= 1 at %s:%d.\n", - str.c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System task `%s' got %d arguments, expected >= 1.\n", + str.c_str(), int(children.size())); // First argument is the format string AstNode *node_string = children[0]; @@ -239,8 +239,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, case 'x': case 'X': if (next_arg >= GetSize(children)) - log_error("Missing argument for %%%c format specifier in system task `%s' at %s:%d.\n", - cformat, str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Missing argument for %%%c format specifier in system task `%s'.\n", + cformat, str.c_str()); node_arg = children[next_arg++]; while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } @@ -717,8 +717,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, paramname = "\\" + paramname.substr(pos+1); if (current_scope.at(modname)->type != AST_CELL) - log_error("Defparam argument `%s . %s` does not match a cell at %s:%d!\n", - RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Defparam argument `%s . %s` does not match a cell!\n", + RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str()); AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL); paraset->str = paramname; @@ -865,8 +865,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width = std::abs(children[1]->range_left - children[1]->range_right) + 1; if (children[0]->type == AST_REALVALUE) { RTLIL::Const constvalue = children[0]->realAsConst(width); - log_warning("converting real value %e to binary %s at %s:%d.\n", - children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum); + log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", + children[0]->realvalue, log_signal(constvalue)); delete children[0]; children[0] = mkconst_bits(constvalue.bits, sign_hint); did_something = true; @@ -1095,8 +1095,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { for (size_t i = 0; i < children.size(); i++) if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM) - log_error("Local declaration in unnamed block at %s:%d is an unsupported SystemVerilog feature!\n", - children[i]->filename.c_str(), children[i]->linenum); + log_file_error(children[i]->filename, children[i]->linenum, "Local declaration in unnamed block is an unsupported SystemVerilog feature!\n"); } // transform block with name @@ -1285,8 +1284,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_PRIMITIVE) { if (children.size() < 2) - log_error("Insufficient number of arguments for primitive `%s' at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Insufficient number of arguments for primitive `%s'!\n", + str.c_str()); std::vector children_list; for (auto child : children) { @@ -1301,8 +1300,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1") { if (children_list.size() != 3) - log_error("Invalid number of arguments for primitive `%s' at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Invalid number of arguments for primitive `%s'!\n", + str.c_str()); std::vector z_const(1, RTLIL::State::Sz); @@ -1387,8 +1386,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (left_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", - str.c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", + str.c_str()); result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; } did_something = true; @@ -1737,12 +1736,12 @@ skip_dynamic_range_lvalue_expansion:; int num_steps = 1; if (GetSize(children) != 1 && GetSize(children) != 2) - log_error("System function %s got %d arguments, expected 1 or 2 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n", + RTLIL::unescape_id(str).c_str(), int(children.size())); if (!current_always_clocked) - log_error("System function %s is only allowed in clocked blocks at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n", + RTLIL::unescape_id(str).c_str()); if (GetSize(children) == 2) { @@ -1805,12 +1804,12 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell") { if (GetSize(children) != 1) - log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", + RTLIL::unescape_id(str).c_str(), int(children.size())); if (!current_always_clocked) - log_error("System function %s is only allowed in clocked blocks at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n", + RTLIL::unescape_id(str).c_str()); AstNode *present = children.at(0)->clone(); AstNode *past = clone(); @@ -1840,8 +1839,8 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$clog2") { if (children.size() != 1) - log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", + RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *buf = children[0]->clone(); while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } @@ -1865,12 +1864,12 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$size" || str == "\\$bits") { if (str == "\\$bits" && children.size() != 1) - log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", + RTLIL::unescape_id(str).c_str(), int(children.size())); if (str == "\\$size" && children.size() != 1 && children.size() != 2) - log_error("System function %s got %d arguments, expected 1 or 2 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n", + RTLIL::unescape_id(str).c_str(), int(children.size())); int dim = 1; if (str == "\\$size" && children.size() == 2) { @@ -1943,19 +1942,19 @@ skip_dynamic_range_lvalue_expansion:; if (func_with_two_arguments) { if (children.size() != 2) - log_error("System function %s got %d arguments, expected 2 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 2.\n", + RTLIL::unescape_id(str).c_str(), int(children.size())); } else { if (children.size() != 1) - log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", + RTLIL::unescape_id(str).c_str(), int(children.size())); } if (children.size() >= 1) { while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (!children[0]->isConst()) - log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n", + RTLIL::unescape_id(str).c_str()); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; children[0]->detectSignWidth(child_width_hint, child_sign_hint); @@ -1965,8 +1964,8 @@ skip_dynamic_range_lvalue_expansion:; if (children.size() >= 2) { while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (!children[1]->isConst()) - log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n", + RTLIL::unescape_id(str).c_str()); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; children[1]->detectSignWidth(child_width_hint, child_sign_hint); @@ -2053,8 +2052,8 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$readmemh" || str == "\\$readmemb") { if (GetSize(children) < 2 || GetSize(children) > 4) - log_error("System function %s got %d arguments, expected 2-4 at %s:%d.\n", - RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum); + log_file_error(filename, linenum, "System function %s got %d arguments, expected 2-4.\n", + RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *node_filename = children[0]->clone(); while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } @@ -3291,16 +3290,16 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) continue; if (stmt->children.at(1)->type != AST_CONSTANT) - log_error("Non-constant expression in constant function at %s:%d (called from %s:%d). X\n", - stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d). X\n", + fcall->filename.c_str(), fcall->linenum); if (stmt->children.at(0)->type != AST_IDENTIFIER) - log_error("Unsupported composite left hand side in constant function at %s:%d (called from %s:%d).\n", - stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function (called from %s:%d).\n", + fcall->filename.c_str(), fcall->linenum); if (!variables.count(stmt->children.at(0)->str)) - log_error("Assignment to non-local variable in constant function at %s:%d (called from %s:%d).\n", - stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function (called from %s:%d).\n", + fcall->filename.c_str(), fcall->linenum); if (stmt->children.at(0)->children.empty()) { variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size()); @@ -3339,8 +3338,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (cond->simplify(true, false, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) - log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n", - stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n", + fcall->filename.c_str(), fcall->linenum); if (cond->asBool()) { block->children.insert(block->children.begin(), stmt->children.at(1)->clone()); @@ -3360,8 +3359,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (num->simplify(true, false, false, 1, -1, false, true)) { } if (num->type != AST_CONSTANT) - log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n", - stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n", + fcall->filename.c_str(), fcall->linenum); block->children.erase(block->children.begin()); for (int i = 0; i < num->bitsAsConst().as_int(); i++) @@ -3398,8 +3397,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (cond->simplify(true, false, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) - log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n", - stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n", + fcall->filename.c_str(), fcall->linenum); found_match = cond->asBool(); delete cond; @@ -3428,8 +3427,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) continue; } - log_error("Unsupported language construct in constant function at %s:%d (called from %s:%d).\n", - stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function (called from %s:%d).\n", + fcall->filename.c_str(), fcall->linenum); log_abort(); } diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 4a58357bf..7848c626d 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -49,8 +49,7 @@ static int my_decimal_div_by_two(std::vector &digits) int carry = 0; for (size_t i = 0; i < digits.size(); i++) { if (digits[i] >= 10) - log_error("Invalid use of [a-fxz?] in decimal constant at %s:%d.\n", - current_filename.c_str(), get_line_num()); + log_file_error(current_filename, get_line_num(), "Invalid use of [a-fxz?] in decimal constant.\n"); digits[i] += carry * 10; carry = digits[i] % 2; digits[i] /= 2; @@ -105,8 +104,8 @@ static void my_strtobin(std::vector &data, const char *str, int le int bits_per_digit = my_ilog2(base-1); for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) { if (*it > (base-1) && *it < 0xf0) - log_error("Digit larger than %d used in in base-%d constant at %s:%d.\n", - base-1, base, current_filename.c_str(), get_line_num()); + log_file_error(current_filename, get_line_num(), "Digit larger than %d used in in base-%d constant.\n", + base-1, base); for (int i = 0; i < bits_per_digit; i++) { int bitmask = 1 << i; if (*it == 0xf0) @@ -238,4 +237,3 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn } YOSYS_NAMESPACE_END - From 3101b9b8c979f0a4239ccd823932a490b60d128c Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Fri, 20 Jul 2018 18:52:52 -0700 Subject: [PATCH 140/184] Fix remaining log_file_error(); emit dependent file references in new line. There are some places that reference dependent file locations ("this function was called from ..."). These are now in a separate line for ease of jumping to it with the editor (behaves similarly to compilers that emit dependent messages). --- frontends/ast/simplify.cc | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index be53e8527..75dc60c68 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3201,13 +3201,13 @@ void AstNode::replace_variables(std::map &varia int offset = variables.at(str).offset, width = variables.at(str).val.bits.size(); if (!children.empty()) { if (children.size() != 1 || children.at(0)->type != AST_RANGE) - log_error("Memory access in constant function is not supported in %s:%d (called from %s:%d).\n", - filename.c_str(), linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(filename, linenum, "Memory access in constant function is not supported\n%s:%d: ...called from here.\n", + fcall->filename.c_str(), fcall->linenum); children.at(0)->replace_variables(variables, fcall); while (simplify(true, false, false, 1, -1, false, true)) { } if (!children.at(0)->range_valid) - log_error("Non-constant range in %s:%d (called from %s:%d).\n", - filename.c_str(), linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(filename, linenum, "Non-constant range\n%s:%d: ... called from here.\n", + fcall->filename.c_str(), fcall->linenum); offset = min(children.at(0)->range_left, children.at(0)->range_right); width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width); } @@ -3246,8 +3246,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) { while (child->simplify(true, false, false, 1, -1, false, true)) { } if (!child->range_valid) - log_error("Can't determine size of variable %s in %s:%d (called from %s:%d).\n", - child->str.c_str(), child->filename.c_str(), child->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(child->filename, child->linenum, "Can't determine size of variable %s\n%s:%d: ... called from here.\n", + child->str.c_str(), fcall->filename.c_str(), fcall->linenum); variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1); variables[child->str].offset = min(child->range_left, child->range_right); variables[child->str].is_signed = child->is_signed; @@ -3290,15 +3290,15 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) continue; if (stmt->children.at(1)->type != AST_CONSTANT) - log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d). X\n", + log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here. X\n", fcall->filename.c_str(), fcall->linenum); if (stmt->children.at(0)->type != AST_IDENTIFIER) - log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function (called from %s:%d).\n", + log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function\n%s:%d: ... called from here.\n", fcall->filename.c_str(), fcall->linenum); if (!variables.count(stmt->children.at(0)->str)) - log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function (called from %s:%d).\n", + log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function\n%s:%d: ... called from here.\n", fcall->filename.c_str(), fcall->linenum); if (stmt->children.at(0)->children.empty()) { @@ -3306,8 +3306,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) } else { AstNode *range = stmt->children.at(0)->children.at(0); if (!range->range_valid) - log_error("Non-constant range in %s:%d (called from %s:%d).\n", - range->filename.c_str(), range->linenum, fcall->filename.c_str(), fcall->linenum); + log_file_error(range->filename, range->linenum, "Non-constant range\n%s:%d: ... called from here.\n", + fcall->filename.c_str(), fcall->linenum); int offset = min(range->range_left, range->range_right); int width = std::abs(range->range_left - range->range_right) + 1; varinfo_t &v = variables[stmt->children.at(0)->str]; @@ -3338,7 +3338,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (cond->simplify(true, false, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) - log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n", + log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", fcall->filename.c_str(), fcall->linenum); if (cond->asBool()) { @@ -3359,7 +3359,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (num->simplify(true, false, false, 1, -1, false, true)) { } if (num->type != AST_CONSTANT) - log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n", + log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", fcall->filename.c_str(), fcall->linenum); block->children.erase(block->children.begin()); @@ -3397,7 +3397,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (cond->simplify(true, false, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) - log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n", + log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", fcall->filename.c_str(), fcall->linenum); found_match = cond->asBool(); @@ -3427,7 +3427,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) continue; } - log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function (called from %s:%d).\n", + log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function\n%s:%d: ... called from here.\n", fcall->filename.c_str(), fcall->linenum); log_abort(); } From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001 From: Henner Zeller Date: Fri, 20 Jul 2018 23:41:18 -0700 Subject: [PATCH 141/184] Consistent use of 'override' for virtual methods in derived classes. o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) --- CodingReadme | 2 +- backends/aiger/aiger.cc | 4 ++-- backends/blif/blif.cc | 4 ++-- backends/btor/btor.cc | 4 ++-- backends/edif/edif.cc | 4 ++-- backends/firrtl/firrtl.cc | 4 ++-- backends/ilang/ilang_backend.cc | 8 ++++---- backends/intersynth/intersynth.cc | 4 ++-- backends/json/json.cc | 8 ++++---- backends/protobuf/protobuf.cc | 8 ++++---- backends/simplec/simplec.cc | 4 ++-- backends/smt2/smt2.cc | 4 ++-- backends/smv/smv.cc | 4 ++-- backends/spice/spice.cc | 4 ++-- backends/table/table.cc | 4 ++-- backends/verilog/verilog_backend.cc | 4 ++-- examples/cxx-api/evaldemo.cc | 2 +- frontends/ast/ast.h | 8 ++++---- frontends/blif/blifparse.cc | 4 ++-- frontends/ilang/ilang_frontend.cc | 4 ++-- frontends/json/jsonparse.cc | 4 ++-- frontends/liberty/liberty.cc | 4 ++-- frontends/verific/verific.cc | 10 +++++----- frontends/verilog/verilog_frontend.cc | 12 ++++++------ kernel/celledges.h | 6 +++--- kernel/modtools.h | 10 +++++----- kernel/register.cc | 11 +++++------ kernel/register.h | 14 +++++++------- kernel/rtlil.h | 2 +- kernel/satgen.h | 2 +- kernel/yosys.cc | 16 ++++++++-------- kernel/yosys.h | 2 +- manual/CHAPTER_Prog/stubnets.cc | 2 +- manual/PRESENTATION_Prog/my_cmd.cc | 6 +++--- passes/cmds/add.cc | 4 ++-- passes/cmds/blackbox.cc | 4 ++-- passes/cmds/check.cc | 4 ++-- passes/cmds/chformal.cc | 4 ++-- passes/cmds/chtype.cc | 4 ++-- passes/cmds/connect.cc | 4 ++-- passes/cmds/connwrappers.cc | 4 ++-- passes/cmds/copy.cc | 4 ++-- passes/cmds/cover.cc | 4 ++-- passes/cmds/delete.cc | 4 ++-- passes/cmds/design.cc | 6 +++--- passes/cmds/edgetypes.cc | 4 ++-- passes/cmds/logcmd.cc | 4 ++-- passes/cmds/ltp.cc | 4 ++-- passes/cmds/plugin.cc | 4 ++-- passes/cmds/qwp.cc | 4 ++-- passes/cmds/rename.cc | 4 ++-- passes/cmds/scatter.cc | 4 ++-- passes/cmds/scc.cc | 4 ++-- passes/cmds/select.cc | 14 +++++++------- passes/cmds/setattr.cc | 12 ++++++------ passes/cmds/setundef.cc | 4 ++-- passes/cmds/show.cc | 4 ++-- passes/cmds/splice.cc | 4 ++-- passes/cmds/splitnets.cc | 4 ++-- passes/cmds/stat.cc | 4 ++-- passes/cmds/tee.cc | 4 ++-- passes/cmds/torder.cc | 4 ++-- passes/cmds/trace.cc | 17 ++++++++--------- passes/cmds/write_file.cc | 4 ++-- passes/equiv/equiv_add.cc | 4 ++-- passes/equiv/equiv_induct.cc | 4 ++-- passes/equiv/equiv_make.cc | 4 ++-- passes/equiv/equiv_mark.cc | 4 ++-- passes/equiv/equiv_miter.cc | 4 ++-- passes/equiv/equiv_purge.cc | 4 ++-- passes/equiv/equiv_remove.cc | 4 ++-- passes/equiv/equiv_simple.cc | 4 ++-- passes/equiv/equiv_status.cc | 4 ++-- passes/equiv/equiv_struct.cc | 4 ++-- passes/fsm/fsm.cc | 4 ++-- passes/fsm/fsm_detect.cc | 4 ++-- passes/fsm/fsm_expand.cc | 4 ++-- passes/fsm/fsm_export.cc | 4 ++-- passes/fsm/fsm_extract.cc | 4 ++-- passes/fsm/fsm_info.cc | 4 ++-- passes/fsm/fsm_map.cc | 4 ++-- passes/fsm/fsm_opt.cc | 4 ++-- passes/fsm/fsm_recode.cc | 4 ++-- passes/hierarchy/hierarchy.cc | 4 ++-- passes/hierarchy/submod.cc | 4 ++-- passes/hierarchy/uniquify.cc | 4 ++-- passes/memory/memory.cc | 4 ++-- passes/memory/memory_bram.cc | 4 ++-- passes/memory/memory_collect.cc | 4 ++-- passes/memory/memory_dff.cc | 4 ++-- passes/memory/memory_map.cc | 4 ++-- passes/memory/memory_memx.cc | 4 ++-- passes/memory/memory_nordff.cc | 4 ++-- passes/memory/memory_share.cc | 4 ++-- passes/memory/memory_unpack.cc | 4 ++-- passes/opt/opt.cc | 4 ++-- passes/opt/opt_clean.cc | 8 ++++---- passes/opt/opt_demorgan.cc | 4 ++-- passes/opt/opt_expr.cc | 4 ++-- passes/opt/opt_merge.cc | 4 ++-- passes/opt/opt_muxtree.cc | 4 ++-- passes/opt/opt_reduce.cc | 4 ++-- passes/opt/opt_rmdff.cc | 4 ++-- passes/opt/rmports.cc | 4 ++-- passes/opt/share.cc | 4 ++-- passes/opt/wreduce.cc | 4 ++-- passes/proc/proc.cc | 4 ++-- passes/proc/proc_arst.cc | 4 ++-- passes/proc/proc_clean.cc | 4 ++-- passes/proc/proc_dff.cc | 4 ++-- passes/proc/proc_dlatch.cc | 4 ++-- passes/proc/proc_init.cc | 4 ++-- passes/proc/proc_mux.cc | 4 ++-- passes/proc/proc_rmdead.cc | 4 ++-- passes/sat/assertpmux.cc | 4 ++-- passes/sat/async2sync.cc | 4 ++-- passes/sat/clk2fflogic.cc | 4 ++-- passes/sat/eval.cc | 4 ++-- passes/sat/expose.cc | 4 ++-- passes/sat/freduce.cc | 4 ++-- passes/sat/miter.cc | 4 ++-- passes/sat/sat.cc | 4 ++-- passes/sat/sim.cc | 4 ++-- passes/techmap/abc.cc | 4 ++-- passes/techmap/aigmap.cc | 4 ++-- passes/techmap/alumacc.cc | 4 ++-- passes/techmap/attrmap.cc | 12 ++++++------ passes/techmap/attrmvcp.cc | 4 ++-- passes/techmap/deminout.cc | 4 ++-- passes/techmap/dff2dffe.cc | 4 ++-- passes/techmap/dff2dffs.cc | 4 ++-- passes/techmap/dffinit.cc | 4 ++-- passes/techmap/dfflibmap.cc | 4 ++-- passes/techmap/dffsr2dff.cc | 4 ++-- passes/techmap/extract.cc | 4 ++-- passes/techmap/extract_counter.cc | 4 ++-- passes/techmap/extract_fa.cc | 4 ++-- passes/techmap/extract_reduce.cc | 4 ++-- passes/techmap/hilomap.cc | 4 ++-- passes/techmap/insbuf.cc | 4 ++-- passes/techmap/iopadmap.cc | 4 ++-- passes/techmap/lut2mux.cc | 4 ++-- passes/techmap/maccmap.cc | 4 ++-- passes/techmap/muxcover.cc | 4 ++-- passes/techmap/nlutmap.cc | 4 ++-- passes/techmap/pmuxtree.cc | 4 ++-- passes/techmap/shregmap.cc | 4 ++-- passes/techmap/simplemap.cc | 4 ++-- passes/techmap/techmap.cc | 8 ++++---- passes/techmap/tribuf.cc | 4 ++-- passes/techmap/zinit.cc | 4 ++-- passes/tests/test_abcloop.cc | 4 ++-- passes/tests/test_autotb.cc | 4 ++-- passes/tests/test_cell.cc | 4 ++-- techlibs/achronix/synth_achronix.cc | 8 ++++---- techlibs/common/prep.cc | 8 ++++---- techlibs/common/synth.cc | 8 ++++---- techlibs/coolrunner2/coolrunner2_sop.cc | 4 ++-- techlibs/coolrunner2/synth_coolrunner2.cc | 8 ++++---- techlibs/easic/synth_easic.cc | 8 ++++---- techlibs/ecp5/synth_ecp5.cc | 8 ++++---- techlibs/gowin/synth_gowin.cc | 8 ++++---- techlibs/greenpak4/greenpak4_dffinv.cc | 4 ++-- techlibs/greenpak4/synth_greenpak4.cc | 8 ++++---- techlibs/ice40/ice40_ffinit.cc | 4 ++-- techlibs/ice40/ice40_ffssr.cc | 4 ++-- techlibs/ice40/ice40_opt.cc | 4 ++-- techlibs/ice40/synth_ice40.cc | 8 ++++---- techlibs/intel/synth_intel.cc | 12 ++++++------ techlibs/xilinx/synth_xilinx.cc | 4 ++-- 170 files changed, 414 insertions(+), 416 deletions(-) diff --git a/CodingReadme b/CodingReadme index 5800e30c3..4ab132a63 100644 --- a/CodingReadme +++ b/CodingReadme @@ -21,7 +21,7 @@ Here is a the C++ code for a "hello_world" Yosys command (hello.cc): struct HelloWorldPass : public Pass { HelloWorldPass() : Pass("hello_world") { } - virtual void execute(vector, Design*) { + void execute(vector, Design*) override { log("Hello World!\n"); } } HelloWorldPass; diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 526e50a49..c323691a3 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -657,7 +657,7 @@ struct AigerWriter struct AigerBackend : public Backend { AigerBackend() : Backend("aiger", "write design to AIGER file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -690,7 +690,7 @@ struct AigerBackend : public Backend { log(" like -map, but more verbose\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool ascii_mode = false; bool zinit_mode = false; diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index e4509e0d0..0db5ff27c 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -464,7 +464,7 @@ struct BlifDumper struct BlifBackend : public Backend { BlifBackend() : Backend("blif", "write design to BLIF file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -534,7 +534,7 @@ struct BlifBackend : public Backend { log(" do not write definitions for the $true, $false and $undef wires.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string top_module_name; std::string buf_type, buf_in, buf_out; diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 61a2f8ba3..58d2a8625 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1076,7 +1076,7 @@ struct BtorWorker struct BtorBackend : public Backend { BtorBackend() : Backend("btor", "write design to BTOR file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1091,7 +1091,7 @@ struct BtorBackend : public Backend { log(" Output only a single bad property for all asserts\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool verbose = false, single_bad = false; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index a6534b911..5f9ec54fd 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -90,7 +90,7 @@ struct EdifNames struct EdifBackend : public Backend { EdifBackend() : Backend("edif", "write design to EDIF netlist file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -116,7 +116,7 @@ struct EdifBackend : public Backend { log("is targeted.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing EDIF backend.\n"); std::string top_module_name; diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 06cbc9b2b..4f56f498c 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -527,7 +527,7 @@ struct FirrtlWorker struct FirrtlBackend : public Backend { FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -536,7 +536,7 @@ struct FirrtlBackend : public Backend { log("Write a FIRRTL netlist of the current design.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 1f7f12361..4c58ea087 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -382,7 +382,7 @@ PRIVATE_NAMESPACE_BEGIN struct IlangBackend : public Backend { IlangBackend() : Backend("ilang", "write design to ilang file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -395,7 +395,7 @@ struct IlangBackend : public Backend { log(" only write selected parts of the design.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool selected = false; @@ -422,7 +422,7 @@ struct IlangBackend : public Backend { struct DumpPass : public Pass { DumpPass() : Pass("dump", "print parts of the design in ilang format") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -445,7 +445,7 @@ struct DumpPass : public Pass { log(" like -outfile but append instead of overwrite\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string filename; bool flag_m = false, flag_n = false, append = false; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 34cb52fb4..2eb08dbe9 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -46,7 +46,7 @@ static std::string netname(std::set &conntypes_code, std::set args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing INTERSYNTH backend.\n"); log_push(); diff --git a/backends/json/json.cc b/backends/json/json.cc index d3b7077a2..5a87859a0 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -250,7 +250,7 @@ struct JsonWriter struct JsonBackend : public Backend { JsonBackend() : Backend("json", "write design to a JSON file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -458,7 +458,7 @@ struct JsonBackend : public Backend { log("format. A program processing this format must ignore all unknown fields.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool aig_mode = false; @@ -482,7 +482,7 @@ struct JsonBackend : public Backend { struct JsonPass : public Pass { JsonPass() : Pass("json", "write design in JSON format") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -499,7 +499,7 @@ struct JsonPass : public Pass { log("See 'help write_json' for a description of the JSON format used.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string filename; bool aig_mode = false; diff --git a/backends/protobuf/protobuf.cc b/backends/protobuf/protobuf.cc index 9a6fedee7..f56147cef 100644 --- a/backends/protobuf/protobuf.cc +++ b/backends/protobuf/protobuf.cc @@ -231,7 +231,7 @@ struct ProtobufDesignSerializer struct ProtobufBackend : public Backend { ProtobufBackend(): Backend("protobuf", "write design to a Protocol Buffer file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -249,7 +249,7 @@ struct ProtobufBackend : public Backend { log("Yosys source code distribution.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool aig_mode = false; bool text_mode = false; @@ -286,7 +286,7 @@ struct ProtobufBackend : public Backend { struct ProtobufPass : public Pass { ProtobufPass() : Pass("protobuf", "write design in Protobuf format") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -307,7 +307,7 @@ struct ProtobufPass : public Pass { log("Yosys source code distribution.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string filename; bool aig_mode = false; diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index c9656caff..349bc5a6d 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -742,7 +742,7 @@ struct SimplecWorker struct SimplecBackend : public Backend { SimplecBackend() : Backend("simplec", "convert design to simple C code") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -761,7 +761,7 @@ struct SimplecBackend : public Backend { log("THIS COMMAND IS UNDER CONSTRUCTION\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { reserved_cids.clear(); id2cid.clear(); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index ca1ceacc7..e2777ae04 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1251,7 +1251,7 @@ struct Smt2Worker struct Smt2Backend : public Backend { Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1407,7 +1407,7 @@ struct Smt2Backend : public Backend { log("from non-zero to zero in the test design.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::ifstream template_f; bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false, statedt = false; diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 768969e6b..b8383412b 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -675,7 +675,7 @@ struct SmvWorker struct SmvBackend : public Backend { SmvBackend() : Backend("smv", "write design to SMV file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -693,7 +693,7 @@ struct SmvBackend : public Backend { log("THIS COMMAND IS UNDER CONSTRUCTION\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::ifstream template_f; bool verbose = false; diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 4101cbf98..b6a3f1e77 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -132,7 +132,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De struct SpiceBackend : public Backend { SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -161,7 +161,7 @@ struct SpiceBackend : public Backend { log(" set the specified module as design top module\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string top_module_name; RTLIL::Module *top_module = NULL; diff --git a/backends/table/table.cc b/backends/table/table.cc index 27b7edfff..979273dd3 100644 --- a/backends/table/table.cc +++ b/backends/table/table.cc @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct TableBackend : public Backend { TableBackend() : Backend("table", "write design as connectivity table") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -48,7 +48,7 @@ struct TableBackend : public Backend { log("module inputs and outputs are output using cell type and port '-' and with\n"); log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing TABLE backend.\n"); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index b50dc12af..44e4e5f97 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1482,7 +1482,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) struct VerilogBackend : public Backend { VerilogBackend() : Backend("verilog", "write design to Verilog file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1550,7 +1550,7 @@ struct VerilogBackend : public Backend { log("this command is called on a design with RTLIL processes.\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing Verilog backend.\n"); diff --git a/examples/cxx-api/evaldemo.cc b/examples/cxx-api/evaldemo.cc index e5cc8d8e7..34373487d 100644 --- a/examples/cxx-api/evaldemo.cc +++ b/examples/cxx-api/evaldemo.cc @@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass { EvalDemoPass() : Pass("evaldemo") { } - virtual void execute(vector, Design *design) + void execute(vector, Design *design) YS_OVERRIDE { Module *module = design->top_module(); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 756629aca..ed784e831 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf @@ -282,9 +282,9 @@ namespace AST struct AstModule : RTLIL::Module { AstNode *ast; bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; - virtual ~AstModule(); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail); - virtual RTLIL::Module *clone() const; + ~AstModule() YS_OVERRIDE; + RTLIL::IdString derive(RTLIL::Design *design, dict parameters, bool mayfail) YS_OVERRIDE; + RTLIL::Module *clone() const YS_OVERRIDE; }; // this must be set by the language frontend before parsing the sources diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index e6bb99954..85ac4ff21 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -550,7 +550,7 @@ error: struct BlifFrontend : public Frontend { BlifFrontend() : Frontend("blif", "read BLIF file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -566,7 +566,7 @@ struct BlifFrontend : public Frontend { log(" multi-bit port 'name'.\n"); log("\n"); } - virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool sop_mode = false; bool wideports = false; diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc index ed6789987..d8783ac1d 100644 --- a/frontends/ilang/ilang_frontend.cc +++ b/frontends/ilang/ilang_frontend.cc @@ -35,7 +35,7 @@ YOSYS_NAMESPACE_BEGIN struct IlangFrontend : public Frontend { IlangFrontend() : Frontend("ilang", "read modules from ilang file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -45,7 +45,7 @@ struct IlangFrontend : public Frontend { log("representation of a design in yosys's internal format.)\n"); log("\n"); } - virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ILANG frontend.\n"); extra_args(f, filename, args, 1); diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 629578c61..82361ea9b 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -494,7 +494,7 @@ void json_import(Design *design, string &modname, JsonNode *node) struct JsonFrontend : public Frontend { JsonFrontend() : Frontend("json", "read JSON file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -504,7 +504,7 @@ struct JsonFrontend : public Frontend { log("for a description of the file format.\n"); log("\n"); } - virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing JSON frontend.\n"); diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index b9e53a4be..0a5bd84de 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -452,7 +452,7 @@ void parse_type_map(std::map> &type_map, struct LibertyFrontend : public Frontend { LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -485,7 +485,7 @@ struct LibertyFrontend : public Frontend { log(" set the specified attribute (to the value 1) on all loaded modules\n"); log("\n"); } - virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_lib = false; bool flag_nooverwrite = false; diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8937cdde8..09bb253f5 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1685,7 +1685,7 @@ bool check_noverific_env() struct VerificPass : public Pass { VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1784,7 +1784,7 @@ struct VerificPass : public Pass { log("\n"); } #ifdef YOSYS_ENABLE_VERIFIC - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (check_noverific_env()) log_cmd_error("This version of Yosys is built without Verific support.\n"); @@ -2162,7 +2162,7 @@ struct VerificPass : public Pass { } #else /* YOSYS_ENABLE_VERIFIC */ - virtual void execute(std::vector, RTLIL::Design *) { + void execute(std::vector, RTLIL::Design *) YS_OVERRIDE { log_cmd_error("This version of Yosys is built without Verific support.\n"); } #endif @@ -2170,7 +2170,7 @@ struct VerificPass : public Pass { struct ReadPass : public Pass { ReadPass() : Pass("read", "load HDL designs") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -2203,7 +2203,7 @@ struct ReadPass : public Pass { log("Add directory to global Verilog/SystemVerilog include directories.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing mode parameter.\n"); diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index be925fea2..911e36112 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -49,7 +49,7 @@ static void error_on_dpi_function(AST::AstNode *node) struct VerilogFrontend : public Frontend { VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -180,7 +180,7 @@ struct VerilogFrontend : public Frontend { log("supported by the Yosys Verilog front-end.\n"); log("\n"); } - virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; @@ -395,7 +395,7 @@ struct VerilogFrontend : public Frontend { struct VerilogDefaults : public Pass { VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -416,7 +416,7 @@ struct VerilogDefaults : public Pass { log("not imply -clear.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design*) + void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE { if (args.size() < 2) cmd_error(args, 1, "Missing argument."); @@ -453,7 +453,7 @@ struct VerilogDefaults : public Pass { struct VerilogDefines : public Pass { VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -469,7 +469,7 @@ struct VerilogDefines : public Pass { log(" undefine the preprocessor symbol 'name'\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/kernel/celledges.h b/kernel/celledges.h index 6aab9ed43..2cc297cb2 100644 --- a/kernel/celledges.h +++ b/kernel/celledges.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf @@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[from_sigbit].insert(to_sigbit); @@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[to_sigbit].insert(from_sigbit); diff --git a/kernel/modtools.h b/kernel/modtools.h index ffcb48d44..409562eb9 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf @@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor #endif } - virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE { log_assert(module == cell->module); @@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor port_add(cell, port, sig); } - virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE { log_assert(module == mod); @@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor } } - virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector&) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector&) YS_OVERRIDE { log_assert(module == mod); auto_reload_module = true; } - virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE + void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE { log_assert(module == mod); auto_reload_module = true; diff --git a/kernel/register.cc b/kernel/register.cc index e30414f44..402a5b3ea 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -615,7 +615,7 @@ static struct CellHelpMessages { struct HelpPass : public Pass { HelpPass() : Pass("help", "display help messages") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" help ................ list all commands\n"); @@ -684,7 +684,7 @@ struct HelpPass : public Pass { fclose(f); } - virtual void execute(std::vector args, RTLIL::Design*) + void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE { if (args.size() == 1) { log("\n"); @@ -768,7 +768,7 @@ struct HelpPass : public Pass { struct EchoPass : public Pass { EchoPass() : Pass("echo", "turning echoing back of commands on and off") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" echo on\n"); @@ -781,7 +781,7 @@ struct EchoPass : public Pass { log("Do not print all commands to log before executing them. (default)\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design*) + void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE { if (args.size() > 2) cmd_error(args, 2, "Unexpected argument."); @@ -806,10 +806,9 @@ struct MinisatSatSolver : public SatSolver { MinisatSatSolver() : SatSolver("minisat") { yosys_satsolver = this; } - virtual ezSAT *create() YS_OVERRIDE { + ezSAT *create() YS_OVERRIDE { return new ezMiniSAT(); } } MinisatSatSolver; YOSYS_NAMESPACE_END - diff --git a/kernel/register.h b/kernel/register.h index 8024c56a0..c74029823 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf @@ -88,9 +88,9 @@ struct Frontend : Pass std::string frontend_name; Frontend(std::string name, std::string short_help = "** document me **"); - virtual void run_register() YS_OVERRIDE; - virtual ~Frontend(); - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; + void run_register() YS_OVERRIDE; + ~Frontend() YS_OVERRIDE; + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; static std::vector next_args; @@ -104,9 +104,9 @@ struct Backend : Pass { std::string backend_name; Backend(std::string name, std::string short_help = "** document me **"); - virtual void run_register() YS_OVERRIDE; - virtual ~Backend(); - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; + void run_register() YS_OVERRIDE; + ~Backend() YS_OVERRIDE; + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; void extra_args(std::ostream *&f, std::string &filename, std::vector args, size_t argidx); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 54d0b8c22..027faf416 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf diff --git a/kernel/satgen.h b/kernel/satgen.h index 8d760fff7..210cca3f3 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 750a154e6..2a8ab2005 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -636,7 +636,7 @@ extern Tcl_Interp *yosys_get_tcl_interp() struct TclPass : public Pass { TclPass() : Pass("tcl", "execute a TCL script file") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" tcl \n"); log("\n"); @@ -649,7 +649,7 @@ struct TclPass : public Pass { log("in order to avoid a name collision with the built in commands.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing script file.\n"); if (args.size() > 2) @@ -1111,7 +1111,7 @@ void shell(RTLIL::Design *design) struct ShellPass : public Pass { ShellPass() : Pass("shell", "enter interactive command mode") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" shell\n"); log("\n"); @@ -1143,7 +1143,7 @@ struct ShellPass : public Pass { log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { extra_args(args, 1, design, false); shell(design); } @@ -1152,7 +1152,7 @@ struct ShellPass : public Pass { #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) struct HistoryPass : public Pass { HistoryPass() : Pass("history", "show last interactive commands") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" history\n"); log("\n"); @@ -1161,7 +1161,7 @@ struct HistoryPass : public Pass { log("from executed scripts.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { extra_args(args, 1, design, false); #ifdef YOSYS_ENABLE_READLINE for(HIST_ENTRY **list = history_list(); *list != NULL; list++) @@ -1176,7 +1176,7 @@ struct HistoryPass : public Pass { struct ScriptCmdPass : public Pass { ScriptCmdPass() : Pass("script", "execute commands from script file") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" script [:]\n"); log("\n"); @@ -1191,7 +1191,7 @@ struct ScriptCmdPass : public Pass { log("marked with that label (until the next label) is executed.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing script file.\n"); else if (args.size() == 2) diff --git a/kernel/yosys.h b/kernel/yosys.h index 14cbcd610..c9f973318 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index eb77bd404..8123e63db 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -98,7 +98,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // each pass contains a singleton object that is derived from Pass struct StubnetsPass : public Pass { StubnetsPass() : Pass("stubnets") { } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { // variables to mirror information from passed options bool report_bits = 0; diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc index d99bfe1e8..5d9a7e13b 100644 --- a/manual/PRESENTATION_Prog/my_cmd.cc +++ b/manual/PRESENTATION_Prog/my_cmd.cc @@ -6,7 +6,7 @@ PRIVATE_NAMESPACE_BEGIN struct MyPass : public Pass { MyPass() : Pass("my_cmd", "just a simple test") { } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log("Arguments to my_cmd:\n"); for (auto &arg : args) @@ -22,7 +22,7 @@ struct MyPass : public Pass { struct Test1Pass : public Pass { Test1Pass() : Pass("test1", "creating the absval module") { } - virtual void execute(std::vector, RTLIL::Design *design) + void execute(std::vector, RTLIL::Design *design) YS_OVERRIDE { if (design->has("\\absval") != 0) log_error("A module with the name absval already exists!\n"); @@ -49,7 +49,7 @@ struct Test1Pass : public Pass { struct Test2Pass : public Pass { Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { } - virtual void execute(std::vector, RTLIL::Design *design) + void execute(std::vector, RTLIL::Design *design) YS_OVERRIDE { if (design->selection_stack.back().empty()) log_cmd_error("This command can't operator on an empty selection!\n"); diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index e698926f9..cfccca966 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -83,7 +83,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n struct AddPass : public Pass { AddPass() : Pass("add", "add objects to the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -106,7 +106,7 @@ struct AddPass : public Pass { log("selected modules.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string command; std::string arg_name; diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc index 497b35f5c..6094f8f16 100644 --- a/passes/cmds/blackbox.cc +++ b/passes/cmds/blackbox.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct BlackboxPass : public Pass { BlackboxPass() : Pass("blackbox", "change type of cells in the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -34,7 +34,7 @@ struct BlackboxPass : public Pass { log("module attribute).\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index bb8fe6856..64697c134 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct CheckPass : public Pass { CheckPass() : Pass("check", "check for obvious problems in the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -51,7 +51,7 @@ struct CheckPass : public Pass { log("problems are found in the current design.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { int counter = 0; bool noinit = false; diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index a8c1fef85..522758eae 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct ChformalPass : public Pass { ChformalPass() : Pass("chformal", "change formal constraints of the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -62,7 +62,7 @@ struct ChformalPass : public Pass { log(" change the roles of cells as indicated. this options can be combined\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool assert2assume = false; bool assume2assert = false; diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc index 90d51667c..979aeadd4 100644 --- a/passes/cmds/chtype.cc +++ b/passes/cmds/chtype.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct ChtypePass : public Pass { ChtypePass() : Pass("chtype", "change type of cells in the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -40,7 +40,7 @@ struct ChtypePass : public Pass { log("\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { IdString set_type; dict map_types; diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 52611cf44..d480b79ac 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -43,7 +43,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & struct ConnectPass : public Pass { ConnectPass() : Pass("connect", "create or remove connections") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -75,7 +75,7 @@ struct ConnectPass : public Pass { log("This command does not operate on module with processes.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { RTLIL::Module *module = NULL; for (auto &it : design->modules_) { diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 1ea48b7eb..5a15cbbaf 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -150,7 +150,7 @@ struct ConnwrappersWorker struct ConnwrappersPass : public Pass { ConnwrappersPass() : Pass("connwrappers", "match width of input-output port pairs") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -172,7 +172,7 @@ struct ConnwrappersPass : public Pass { log("The options -signed, -unsigned, and -port can be specified multiple times.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { ConnwrappersWorker worker; diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index fb863512b..acd2dba52 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct CopyPass : public Pass { CopyPass() : Pass("copy", "copy modules in the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -36,7 +36,7 @@ struct CopyPass : public Pass { log("by this command.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() != 3) log_cmd_error("Invalid number of arguments!\n"); diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index ef4f3f7d0..0ec747671 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -35,7 +35,7 @@ PRIVATE_NAMESPACE_BEGIN struct CoverPass : public Pass { CoverPass() : Pass("cover", "print code coverage counters") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -83,7 +83,7 @@ struct CoverPass : public Pass { log("Coverage counters are only available in Yosys for Linux.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector out_files; std::vector patterns; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 6d51d30e7..f8d91ea48 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct DeletePass : public Pass { DeletePass() : Pass("delete", "delete objects in the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -40,7 +40,7 @@ struct DeletePass : public Pass { log("selected wires, thus 'deleting' module ports.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_input = false; bool flag_output = false; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 490c8dde5..172addcc1 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -27,7 +27,7 @@ std::vector pushed_designs; struct DesignPass : public Pass { DesignPass() : Pass("design", "save, restore and reset current design") { } - virtual ~DesignPass() { + ~DesignPass() YS_OVERRIDE { for (auto &it : saved_designs) delete it.second; saved_designs.clear(); @@ -35,7 +35,7 @@ struct DesignPass : public Pass { delete it; pushed_designs.clear(); } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -94,7 +94,7 @@ struct DesignPass : public Pass { log("between calls to 'read_verilog'. This command resets this memory.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool got_mode = false; bool reset_mode = false; diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc index 7b75a009f..58ed6457d 100644 --- a/passes/cmds/edgetypes.cc +++ b/passes/cmds/edgetypes.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct EdgetypePass : public Pass { EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct EdgetypePass : public Pass { log("is a 4-tuple of source and sink cell type and port name.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc index 85386f3d2..522e1089d 100644 --- a/passes/cmds/logcmd.cc +++ b/passes/cmds/logcmd.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct LogPass : public Pass { LogPass() : Pass("log", "print text and log files") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -52,7 +52,7 @@ struct LogPass : public Pass { log(" do not append a newline\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design*) + void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE { size_t argidx; bool to_stdout = false; diff --git a/passes/cmds/ltp.cc b/passes/cmds/ltp.cc index 42dc794ec..05701710b 100644 --- a/passes/cmds/ltp.cc +++ b/passes/cmds/ltp.cc @@ -141,7 +141,7 @@ struct LtpWorker struct LtpPass : public Pass { LtpPass() : Pass("ltp", "print longest topological path") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -154,7 +154,7 @@ struct LtpPass : public Pass { log(" automatically exclude FF cell types\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool noff = false; diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 828c671de..aa6d5b6cc 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -58,7 +58,7 @@ void load_plugin(std::string, std::vector) struct PluginPass : public Pass { PluginPass() : Pass("plugin", "load and list loaded plugins") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -76,7 +76,7 @@ struct PluginPass : public Pass { log(" List loaded plugins\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string plugin_filename; std::vector plugin_aliases; diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc index f2dfa760e..1c64a7b77 100644 --- a/passes/cmds/qwp.cc +++ b/passes/cmds/qwp.cc @@ -778,7 +778,7 @@ struct QwpWorker struct QwpPass : public Pass { QwpPass() : Pass("qwp", "quadratic wirelength placer") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -808,7 +808,7 @@ struct QwpPass : public Pass { log("dense matrix operations. It is only a toy-placer for small circuits.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { QwpConfig config; xorshift32_state = 123456789; diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 6a002869b..dce576fdf 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -54,7 +54,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: struct RenamePass : public Pass { RenamePass() : Pass("rename", "rename object in the design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -81,7 +81,7 @@ struct RenamePass : public Pass { log("Rename top module.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string pattern_prefix = "_", pattern_suffix = "_"; bool flag_enumerate = false; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index f083e1f67..7123ba9fb 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct ScatterPass : public Pass { ScatterPass() : Pass("scatter", "add additional intermediate nets") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -41,7 +41,7 @@ struct ScatterPass : public Pass { log("Use the opt_clean command to get rid of the additional nets.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { CellTypes ct(design); extra_args(args, 1, design); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 76363e051..99f4fbae8 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -218,7 +218,7 @@ struct SccWorker struct SccPass : public Pass { SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -255,7 +255,7 @@ struct SccPass : public Pass { log(" that are part of a found logic loop\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::map setAttr; bool allCellTypes = false; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index a0720797f..d97aa2b37 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -950,7 +950,7 @@ PRIVATE_NAMESPACE_BEGIN struct SelectPass : public Pass { SelectPass() : Pass("select", "modify and view the list of selected objects") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -964,7 +964,7 @@ struct SelectPass : public Pass { log("list of selected objects.\n"); log("\n"); log("Note that many commands support an optional [selection] argument that can be\n"); - log("used to override the global selection for the command. The syntax of this\n"); + log("used to YS_OVERRIDE the global selection for the command. The syntax of this\n"); log("optional argument is identical to the syntax of the argument\n"); log("described here.\n"); log("\n"); @@ -1167,7 +1167,7 @@ struct SelectPass : public Pass { log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool add_mode = false; bool del_mode = false; @@ -1470,7 +1470,7 @@ struct SelectPass : public Pass { struct CdPass : public Pass { CdPass() : Pass("cd", "a shortcut for 'select -module '") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1496,7 +1496,7 @@ struct CdPass : public Pass { log("This is just a shortcut for 'select -clear'.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() != 1 && args.size() != 2) log_cmd_error("Invalid number of arguments.\n"); @@ -1578,7 +1578,7 @@ static void log_matches(const char *title, Module *module, T list) struct LsPass : public Pass { LsPass() : Pass("ls", "list modules or objects in modules") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1589,7 +1589,7 @@ struct LsPass : public Pass { log("When an active module is selected, this prints a list of objects in the module.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { size_t argidx = 1; extra_args(args, argidx, design); diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 689e3148b..d38a6b3da 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -56,7 +56,7 @@ static void do_setunset(dict &attrs, const std::v struct SetattrPass : public Pass { SetattrPass() : Pass("setattr", "set/unset attributes on objects") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -69,7 +69,7 @@ struct SetattrPass : public Pass { log("instead of objects within modules.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector setunset_list; bool flag_mod = false; @@ -130,7 +130,7 @@ struct SetattrPass : public Pass { struct SetparamPass : public Pass { SetparamPass() : Pass("setparam", "set/unset parameters on objects") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -142,7 +142,7 @@ struct SetparamPass : public Pass { log("The -type option can be used to change the cell type of the selected cells.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { vector setunset_list; string new_cell_type; @@ -188,7 +188,7 @@ struct SetparamPass : public Pass { struct ChparamPass : public Pass { ChparamPass() : Pass("chparam", "re-evaluate modules with new parameters") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -203,7 +203,7 @@ struct ChparamPass : public Pass { log("List the available parameters of the selected modules.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector setunset_list; dict new_parameters; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 3a3ebedf1..0c51c3f06 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -79,7 +79,7 @@ struct SetundefWorker struct SetundefPass : public Pass { SetundefPass() : Pass("setundef", "replace undef values with defined constants") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -113,7 +113,7 @@ struct SetundefPass : public Pass { log(" also create/update init values for flip-flops\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool got_value = false; bool undriven_mode = false; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 56e1122bf..ec04418fa 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -573,7 +573,7 @@ struct ShowWorker struct ShowPass : public Pass { ShowPass() : Pass("show", "generate schematics using graphviz") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -655,7 +655,7 @@ struct ShowPass : public Pass { log("the 'show' command is executed.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Generating Graphviz representation of design.\n"); log_push(); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 7418ec4d2..bafafca4e 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -247,7 +247,7 @@ struct SpliceWorker struct SplicePass : public Pass { SplicePass() : Pass("splice", "create explicit splicing cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -288,7 +288,7 @@ struct SplicePass : public Pass { log("by selected wires are rewired.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool sel_by_cell = false; bool sel_by_wire = false; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 5e37fc597..f5a1f17b3 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -87,7 +87,7 @@ struct SplitnetsWorker struct SplitnetsPass : public Pass { SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -109,7 +109,7 @@ struct SplitnetsPass : public Pass { log(" and split nets so that no driver drives only part of a net.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_ports = false; bool flag_driver = false; diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index f1d958a1a..54f4ea817 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -209,7 +209,7 @@ void read_liberty_cellarea(dict &cell_area, string liberty_fil struct StatPass : public Pass { StatPass() : Pass("stat", "print some statistics") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -231,7 +231,7 @@ struct StatPass : public Pass { log(" e.g. $add_8 for an 8 bit wide $add cell.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Printing statistics.\n"); diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index b68c089e9..ff80f3859 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct TeePass : public Pass { TeePass() : Pass("tee", "redirect command output to file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -49,7 +49,7 @@ struct TeePass : public Pass { log(" Add/subract INT from the -v setting for this command.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector backup_log_files, files_to_close; int backup_log_verbose_level = log_verbose_level; diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc index 56223610d..3c0eac8de 100644 --- a/passes/cmds/torder.cc +++ b/passes/cmds/torder.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct TorderPass : public Pass { TorderPass() : Pass("torder", "print cells in topological order") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -43,7 +43,7 @@ struct TorderPass : public Pass { log(" are not used in topological sorting. this option deactivates that.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool noautostop = false; dict> stop_db; diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index 1a5f873ff..f5305cde9 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -25,34 +25,34 @@ PRIVATE_NAMESPACE_BEGIN struct TraceMonitor : public RTLIL::Monitor { - virtual void notify_module_add(RTLIL::Module *module) YS_OVERRIDE + void notify_module_add(RTLIL::Module *module) YS_OVERRIDE { log("#TRACE# Module add: %s\n", log_id(module)); } - virtual void notify_module_del(RTLIL::Module *module) YS_OVERRIDE + void notify_module_del(RTLIL::Module *module) YS_OVERRIDE { log("#TRACE# Module delete: %s\n", log_id(module)); } - virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE { log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } - virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE + void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE { log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); } - virtual void notify_connect(RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + void notify_connect(RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE { log("#TRACE# New connections in module %s:\n", log_id(module)); for (auto &sigsig : sigsig_vec) log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); } - virtual void notify_blackout(RTLIL::Module *module) YS_OVERRIDE + void notify_blackout(RTLIL::Module *module) YS_OVERRIDE { log("#TRACE# Blackout in module %s:\n", log_id(module)); } @@ -60,7 +60,7 @@ struct TraceMonitor : public RTLIL::Monitor struct TracePass : public Pass { TracePass() : Pass("trace", "redirect command output to file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -70,7 +70,7 @@ struct TracePass : public Pass { log("the design in real time.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -95,4 +95,3 @@ struct TracePass : public Pass { } TracePass; PRIVATE_NAMESPACE_END - diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc index 70892a945..9613b462b 100644 --- a/passes/cmds/write_file.cc +++ b/passes/cmds/write_file.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct WriteFileFrontend : public Frontend { WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -44,7 +44,7 @@ struct WriteFileFrontend : public Frontend { log(" EOT\n"); log("\n"); } - virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design*) + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design*) YS_OVERRIDE { bool append_mode = false; std::string output_filename; diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 0494a724f..71599f46e 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct EquivAddPass : public Pass { EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -39,7 +39,7 @@ struct EquivAddPass : public Pass { log("This command adds $equiv cells for the ports of the specified cells.\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { bool try_mode = false; diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index c958c3de4..bcc68d6d2 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -162,7 +162,7 @@ struct EquivInductWorker struct EquivInductPass : public Pass { EquivInductPass() : Pass("equiv_induct", "proving $equiv cells using temporal induction") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -192,7 +192,7 @@ struct EquivInductPass : public Pass { log("after reset.\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { int success_counter = 0; bool model_undef = false; diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index b20463777..b1f88d55e 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -390,7 +390,7 @@ struct EquivMakeWorker struct EquivMakePass : public Pass { EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -415,7 +415,7 @@ struct EquivMakePass : public Pass { log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { EquivMakeWorker worker; worker.ct.setup(design); diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc index 22c501763..135eaf145 100644 --- a/passes/equiv/equiv_mark.cc +++ b/passes/equiv/equiv_mark.cc @@ -204,7 +204,7 @@ struct EquivMarkWorker struct EquivMarkPass : public Pass { EquivMarkPass() : Pass("equiv_mark", "mark equivalence checking regions") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -216,7 +216,7 @@ struct EquivMarkPass : public Pass { log("wires and cells.\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { log_header(design, "Executing EQUIV_MARK pass.\n"); diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index eb2e5a171..e06f9515b 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -261,7 +261,7 @@ struct EquivMiterWorker struct EquivMiterPass : public Pass { EquivMiterPass() : Pass("equiv_miter", "extract miter from equiv circuit") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -282,7 +282,7 @@ struct EquivMiterPass : public Pass { log(" Create compare logic that handles undefs correctly\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { EquivMiterWorker worker; worker.ct.setup(design); diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index f8d3cd0af..18b3e7d36 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -176,7 +176,7 @@ struct EquivPurgeWorker struct EquivPurgePass : public Pass { EquivPurgePass() : Pass("equiv_purge", "purge equivalence checking module") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -187,7 +187,7 @@ struct EquivPurgePass : public Pass { log("ports as needed.\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { log_header(design, "Executing EQUIV_PURGE pass.\n"); diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc index 770497a51..c5c28c7d9 100644 --- a/passes/equiv/equiv_remove.cc +++ b/passes/equiv/equiv_remove.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct EquivRemovePass : public Pass { EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -40,7 +40,7 @@ struct EquivRemovePass : public Pass { log(" keep gate circuit\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { bool mode_gold = false; bool mode_gate = false; diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index e69e17ac6..c2fab26f2 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -273,7 +273,7 @@ struct EquivSimpleWorker struct EquivSimplePass : public Pass { EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -298,7 +298,7 @@ struct EquivSimplePass : public Pass { log(" the max. number of time steps to be considered (default = 1)\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { bool verbose = false, short_cones = false, model_undef = false, nogroup = false; int success_counter = 0; diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc index 7b9230b35..b4a93ccf5 100644 --- a/passes/equiv/equiv_status.cc +++ b/passes/equiv/equiv_status.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct EquivStatusPass : public Pass { EquivStatusPass() : Pass("equiv_status", "print status of equivalent checking module") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -36,7 +36,7 @@ struct EquivStatusPass : public Pass { log(" produce an error if any unproven $equiv cell is found\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { bool assert_mode = false; int unproven_count = 0; diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index c4ced6a71..a7973fd04 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -283,7 +283,7 @@ struct EquivStructWorker struct EquivStructPass : public Pass { EquivStructPass() : Pass("equiv_struct", "structural equivalence checking") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -314,7 +314,7 @@ struct EquivStructPass : public Pass { log(" maximum number of iterations to run before aborting\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { pool fwonly_cells({ "$equiv" }); bool mode_icells = false; diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc index 997558b85..c5cb338ab 100644 --- a/passes/fsm/fsm.cc +++ b/passes/fsm/fsm.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct FsmPass : public Pass { FsmPass() : Pass("fsm", "extract and optimize finite state machines") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -68,7 +68,7 @@ struct FsmPass : public Pass { log(" passed through to fsm_recode pass\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_nomap = false; bool flag_norecode = false; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 9fb5446e7..fc504e98c 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -245,7 +245,7 @@ static void detect_fsm(RTLIL::Wire *wire) struct FsmDetectPass : public Pass { FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -261,7 +261,7 @@ struct FsmDetectPass : public Pass { log("'fsm_encoding' attribute to \"none\".\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 2c344a1c1..c34d0c15c 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -265,7 +265,7 @@ struct FsmExpand struct FsmExpandPass : public Pass { FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -279,7 +279,7 @@ struct FsmExpandPass : public Pass { log("word-wide cells. Call with -full to consider all cells for merging.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool full_mode = false; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 1cbfcfae8..8eb1872f0 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -120,7 +120,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st */ struct FsmExportPass : public Pass { FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -143,7 +143,7 @@ struct FsmExportPass : public Pass { log(" use binary state encoding as state names instead of s0, s1, ...\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { dict::iterator attr_it; std::string arg; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 8a4ee3f26..67551f673 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -401,7 +401,7 @@ static void extract_fsm(RTLIL::Wire *wire) struct FsmExtractPass : public Pass { FsmExtractPass() : Pass("fsm_extract", "extracting FSMs in design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -417,7 +417,7 @@ struct FsmExtractPass : public Pass { log("'opt_clean' pass to eliminate this signal.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index 2cc1a7d53..0548259ee 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN struct FsmInfoPass : public Pass { FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -41,7 +41,7 @@ struct FsmInfoPass : public Pass { log("pass so that this information is included in the synthesis log file.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 3edaf84d2..90c958912 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -322,7 +322,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) struct FsmMapPass : public Pass { FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -331,7 +331,7 @@ struct FsmMapPass : public Pass { log("This pass translates FSM cells to flip-flops and logic.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 5b1da44fc..3a6ac2746 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -323,7 +323,7 @@ PRIVATE_NAMESPACE_BEGIN struct FsmOptPass : public Pass { FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -334,7 +334,7 @@ struct FsmOptPass : public Pass { log("combination with the 'opt_clean' pass (see also 'help fsm').\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index e1bde728f..fa1ff48cc 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -126,7 +126,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs struct FsmRecodePass : public Pass { FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -151,7 +151,7 @@ struct FsmRecodePass : public Pass { log(" .map \n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { FILE *fm_set_fsm_file = NULL; FILE *encfile = NULL; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index e61851481..5df69848e 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -343,7 +343,7 @@ int find_top_mod_score(Design *design, Module *module, dict &db) struct HierarchyPass : public Pass { HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -414,7 +414,7 @@ struct HierarchyPass : public Pass { log("in the current design.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index e9ee4eef9..ec242aa1f 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -269,7 +269,7 @@ struct SubmodWorker struct SubmodPass : public Pass { SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -297,7 +297,7 @@ struct SubmodPass : public Pass { log("with -copy to not modify the source module.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n"); log_push(); diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc index 1da0870f6..c88ecd82e 100644 --- a/passes/hierarchy/uniquify.cc +++ b/passes/hierarchy/uniquify.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct UniquifyPass : public Pass { UniquifyPass() : Pass("uniquify", "create unique copies of modules") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -41,7 +41,7 @@ struct UniquifyPass : public Pass { log("attribute set (the 'top' module is unique implicitly).\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n"); diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc index 947d598be..712bc2537 100644 --- a/passes/memory/memory.cc +++ b/passes/memory/memory.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct MemoryPass : public Pass { MemoryPass() : Pass("memory", "translate memories to basic cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -48,7 +48,7 @@ struct MemoryPass : public Pass { log("or multiport memory blocks if called with the -nomap option.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_nomap = false; bool flag_nordff = false; diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index a7f9cf382..e8552bbcf 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -1120,7 +1120,7 @@ void handle_cell(Cell *cell, const rules_t &rules) struct MemoryBramPass : public Pass { MemoryBramPass() : Pass("memory_bram", "map memories to block rams") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1210,7 +1210,7 @@ struct MemoryBramPass : public Pass { log("the data bits to accommodate the enable pattern of port A.\n"); log("\n"); } - virtual void execute(vector args, Design *design) + void execute(vector args, Design *design) YS_OVERRIDE { rules_t rules; diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index ab66e3fb8..70d98713c 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -246,7 +246,7 @@ static void handle_module(Design *design, Module *module) struct MemoryCollectPass : public Pass { MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -256,7 +256,7 @@ struct MemoryCollectPass : public Pass { log("memory cells.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n"); extra_args(args, 1, design); for (auto &mod_it : design->modules_) diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 6e036397d..32df19174 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -283,7 +283,7 @@ struct MemoryDffWorker struct MemoryDffPass : public Pass { MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -297,7 +297,7 @@ struct MemoryDffPass : public Pass { log(" do not merge registers on read ports\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_wr_only = false; diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index bffeec857..a0b808e56 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -352,7 +352,7 @@ struct MemoryMapWorker struct MemoryMapPass : public Pass { MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -362,7 +362,7 @@ struct MemoryMapPass : public Pass { log("pass to word-wide DFFs and address decoders.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); for (auto mod : design->selected_modules()) diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc index 2b02e2490..958370164 100644 --- a/passes/memory/memory_memx.cc +++ b/passes/memory/memory_memx.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct MemoryMemxPass : public Pass { MemoryMemxPass() : Pass("memory_memx", "emulate vlog sim behavior for mem ports") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -38,7 +38,7 @@ struct MemoryMemxPass : public Pass { log("behavior for out-of-bounds memory reads and writes.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_MEMX pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc index 87ab7c623..ba0361c0f 100644 --- a/passes/memory/memory_nordff.cc +++ b/passes/memory/memory_nordff.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct MemoryNordffPass : public Pass { MemoryNordffPass() : Pass("memory_nordff", "extract read port FFs from memories") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct MemoryNordffPass : public Pass { log("similar to what one would get from calling memory_dff with -nordff.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from $mem).\n"); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index ca09ac52c..172afe0cb 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -726,7 +726,7 @@ struct MemoryShareWorker struct MemorySharePass : public Pass { MemorySharePass() : Pass("memory_share", "consolidate memory ports") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -752,7 +752,7 @@ struct MemorySharePass : public Pass { log("optimizations) such as \"share\" and \"opt_merge\".\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); extra_args(args, 1, design); for (auto module : design->selected_modules()) diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index a0fc31b5e..49ec66792 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -127,7 +127,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module) struct MemoryUnpackPass : public Pass { MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -137,7 +137,7 @@ struct MemoryUnpackPass : public Pass { log("$memwr cells. It is the counterpart to the memory_collect pass.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) { + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); extra_args(args, 1, design); for (auto &mod_it : design->modules_) diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index 021c1a03f..a4aca2fee 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct OptPass : public Pass { OptPass() : Pass("opt", "perform simple optimizations") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -63,7 +63,7 @@ struct OptPass : public Pass { log("\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string opt_clean_args; std::string opt_expr_args; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 25d462ada..c3b13acaf 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -442,7 +442,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool struct OptCleanPass : public Pass { OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -459,7 +459,7 @@ struct OptCleanPass : public Pass { log(" also remove internal nets if they have a public name\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool purge_mode = false; @@ -505,7 +505,7 @@ struct OptCleanPass : public Pass { struct CleanPass : public Pass { CleanPass() : Pass("clean", "remove unused cells and wires") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -520,7 +520,7 @@ struct CleanPass : public Pass { log("in -purge mode between the commands.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool purge_mode = false; diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc index f2af1cb93..1699a6454 100644 --- a/passes/opt/opt_demorgan.cc +++ b/passes/opt/opt_demorgan.cc @@ -169,7 +169,7 @@ void demorgan_worker( struct OptDemorganPass : public Pass { OptDemorganPass() : Pass("opt_demorgan", "Optimize reductions with DeMorgan equivalents") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -179,7 +179,7 @@ struct OptDemorganPass : public Pass { log("overall gate count of the circuit\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n"); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index a54a5c6b8..0ba233c62 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1470,7 +1470,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons struct OptExprPass : public Pass { OptExprPass() : Pass("opt_expr", "perform const folding and simple expression rewriting") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1504,7 +1504,7 @@ struct OptExprPass : public Pass { log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool mux_undef = false; bool mux_bool = false; diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 2aeb514e4..eedf88904 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -341,7 +341,7 @@ struct OptMergeWorker struct OptMergePass : public Pass { OptMergePass() : Pass("opt_merge", "consolidate identical cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -357,7 +357,7 @@ struct OptMergePass : public Pass { log(" Operate on all cell types, not just built-in types.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n"); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index f5ddc2af9..87c7ce9b2 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -449,7 +449,7 @@ struct OptMuxtreeWorker struct OptMuxtreePass : public Pass { OptMuxtreePass() : Pass("opt_muxtree", "eliminate dead trees in multiplexer trees") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -462,7 +462,7 @@ struct OptMuxtreePass : public Pass { log("This pass only operates on completely selected modules without processes.\n"); log("\n"); } - virtual void execute(vector args, RTLIL::Design *design) + void execute(vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n"); extra_args(args, 1, design); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index eb9d02ad5..d99f1ca6a 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -329,7 +329,7 @@ struct OptReduceWorker struct OptReducePass : public Pass { OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -350,7 +350,7 @@ struct OptReducePass : public Pass { log(" alias for -fine\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool do_fine = false; diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index b5edb357b..5880254c1 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -399,7 +399,7 @@ delete_dff: struct OptRmdffPass : public Pass { OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -409,7 +409,7 @@ struct OptRmdffPass : public Pass { log("a constant driver.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { int total_count = 0, total_initdrv = 0; log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n"); diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc index 756be7473..fc1596ebf 100644 --- a/passes/opt/rmports.cc +++ b/passes/opt/rmports.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct RmportsPassPass : public Pass { RmportsPassPass() : Pass("rmports", "remove module ports with no connections") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -39,7 +39,7 @@ struct RmportsPassPass : public Pass { log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n"); diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 22914eaa7..b80280829 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1421,7 +1421,7 @@ struct ShareWorker struct SharePass : public Pass { SharePass() : Pass("share", "perform sat-based resource sharing") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1453,7 +1453,7 @@ struct SharePass : public Pass { log(" Only perform the first N merges, then stop. This is useful for debugging.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { ShareWorkerConfig config; diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 07503fbb3..0164f58d6 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -353,7 +353,7 @@ struct WreduceWorker struct WreducePass : public Pass { WreducePass() : Pass("wreduce", "reduce the word size of operations if possible") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -373,7 +373,7 @@ struct WreducePass : public Pass { log(" flows that use the 'memory_memx' pass.\n"); log("\n"); } - virtual void execute(std::vector args, Design *design) + void execute(std::vector args, Design *design) YS_OVERRIDE { WreduceConfig config; bool opt_memx = false; diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index d5366f266..ef7cb0f71 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct ProcPass : public Pass { ProcPass() : Pass("proc", "translate processes to netlists") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -57,7 +57,7 @@ struct ProcPass : public Pass { log(" executed in -ifx mode.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string global_arst; bool ifxmode = false; diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 216b00ddd..b69eba3f9 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -203,7 +203,7 @@ restart_proc_arst: struct ProcArstPass : public Pass { ProcArstPass() : Pass("proc_arst", "detect asynchronous resets") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -221,7 +221,7 @@ struct ProcArstPass : public Pass { log(" in the 'init' attribute on the net.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string global_arst; bool global_arst_neg = false; diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 7dbabc211..b9e43d1db 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -143,7 +143,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count) struct ProcCleanPass : public Pass { ProcCleanPass() : Pass("proc_clean", "remove empty parts of processes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -153,7 +153,7 @@ struct ProcCleanPass : public Pass { log("if it contains only empty structures.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { int total_count = 0; log_header(design, "Executing PROC_CLEAN pass (remove empty switches from decision trees).\n"); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index f732baa17..519d35cd6 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -370,7 +370,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) struct ProcDffPass : public Pass { ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -380,7 +380,7 @@ struct ProcDffPass : public Pass { log("d-type flip-flop cells.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n"); diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 15200ec12..d9d5dfbed 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -422,7 +422,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) struct ProcDlatchPass : public Pass { ProcDlatchPass() : Pass("proc_dlatch", "extract latches from processes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -432,7 +432,7 @@ struct ProcDlatchPass : public Pass { log("d-type latches.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n"); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 0c8fb83dc..e2dc07e53 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -102,7 +102,7 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc) struct ProcInitPass : public Pass { ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -113,7 +113,7 @@ struct ProcInitPass : public Pass { log("respective wire.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PROC_INIT pass (extract init attributes).\n"); diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 57e131ca5..1329c1fef 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -382,7 +382,7 @@ void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode) struct ProcMuxPass : public Pass { ProcMuxPass() : Pass("proc_mux", "convert decision trees to multiplexers") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -396,7 +396,7 @@ struct ProcMuxPass : public Pass { log(" 'case' expressions and 'if' conditions.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool ifxmode = false; log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n"); diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 5672fb475..7c334e661 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -65,7 +65,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter) struct ProcRmdeadPass : public Pass { ProcRmdeadPass() : Pass("proc_rmdead", "eliminate dead trees in decision trees") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -74,7 +74,7 @@ struct ProcRmdeadPass : public Pass { log("This pass identifies unreachable branches in decision trees and removes them.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n"); diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 63a907671..509cb0ba9 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -181,7 +181,7 @@ struct AssertpmuxWorker struct AssertpmuxPass : public Pass { AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -199,7 +199,7 @@ struct AssertpmuxPass : public Pass { log(" additional constrained and check the $pmux condition always.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_noinit = false; bool flag_always = false; diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index 85933acc2..c92db7118 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Async2syncPass : public Pass { Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -42,7 +42,7 @@ struct Async2syncPass : public Pass { log("Currently only $adff cells are supported by this pass.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { // bool flag_noinit = false; diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 736c6f571..49ec795d3 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Clk2fflogicPass : public Pass { Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -36,7 +36,7 @@ struct Clk2fflogicPass : public Pass { log("multiple clocks.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { // bool flag_noinit = false; diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 09f69cc5c..008cd2dfa 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -360,7 +360,7 @@ struct VlogHammerReporter struct EvalPass : public Pass { EvalPass() : Pass("eval", "evaluate the circuit given an input") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -383,7 +383,7 @@ struct EvalPass : public Pass { log(" then all output ports of the current module are used.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector> sets; std::vector shows, tables; diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index fa8f0c6be..809345486 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -220,7 +220,7 @@ RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width struct ExposePass : public Pass { ExposePass() : Pass("expose", "convert internal signals to module ports") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -257,7 +257,7 @@ struct ExposePass : public Pass { log(" designator for the exposed signal.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool flag_shared = false; bool flag_evert = false; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index a3028bfce..f29631639 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -760,7 +760,7 @@ struct FreduceWorker struct FreducePass : public Pass { FreducePass() : Pass("freduce", "perform functional reduction") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -791,7 +791,7 @@ struct FreducePass : public Pass { log("circuit that is analyzed.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { reduce_counter = 0; reduce_stop_at = 0; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 9e150b60c..d37f1b126 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -358,7 +358,7 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL struct MiterPass : public Pass { MiterPass() : Pass("miter", "automatically create a miter circuit") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -402,7 +402,7 @@ struct MiterPass : public Pass { log(" call 'flatten; opt_expr -keepdc -undriven;;' on the miter circuit.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() > 1 && args[1] == "-equiv") { create_miter_equiv(this, args, design); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 6c0834deb..695a03e15 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -890,7 +890,7 @@ void print_qed() struct SatPass : public Pass { SatPass() : Pass("sat", "solve a SAT problem in the circuit") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1057,7 +1057,7 @@ struct SatPass : public Pass { log(" Like -falsify but do not return an error for timeouts.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::vector> sets, sets_init, prove, prove_x; std::map>> sets_at; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index b49c12529..fadffcdbc 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -745,7 +745,7 @@ struct SimWorker : SimShared struct SimPass : public Pass { SimPass() : Pass("sim", "simulate the circuit") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -787,7 +787,7 @@ struct SimPass : public Pass { log(" enable debug output\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { SimWorker worker; int numcycles = 20; diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 18868c6d7..d2d15a4a9 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1248,7 +1248,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin struct AbcPass : public Pass { AbcPass() : Pass("abc", "use ABC for technology mapping") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1420,7 +1420,7 @@ struct AbcPass : public Pass { log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ABC pass (technology mapping using ABC).\n"); log_push(); diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index b9ac7aded..35df2ff79 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct AigmapPass : public Pass { AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" aigmap [options] [selection]\n"); @@ -37,7 +37,7 @@ struct AigmapPass : public Pass { log(" Enable creation of $_NAND_ cells\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool nand_mode = false; diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 95be7ab3b..dc7d416b0 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -539,7 +539,7 @@ struct AlumaccWorker struct AlumaccPass : public Pass { AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -549,7 +549,7 @@ struct AlumaccPass : public Pass { log("and $macc cells.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n"); diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index dec81d216..0b5576b06 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -81,7 +81,7 @@ struct AttrmapAction { struct AttrmapTocase : AttrmapAction { string name; - virtual bool apply(IdString &id, Const&) { + bool apply(IdString &id, Const&) YS_OVERRIDE { if (match_name(name, id, true)) id = RTLIL::escape_id(name); return true; @@ -90,7 +90,7 @@ struct AttrmapTocase : AttrmapAction { struct AttrmapRename : AttrmapAction { string old_name, new_name; - virtual bool apply(IdString &id, Const&) { + bool apply(IdString &id, Const&) YS_OVERRIDE { if (match_name(old_name, id)) id = RTLIL::escape_id(new_name); return true; @@ -101,7 +101,7 @@ struct AttrmapMap : AttrmapAction { bool imap; string old_name, new_name; string old_value, new_value; - virtual bool apply(IdString &id, Const &val) { + bool apply(IdString &id, Const &val) YS_OVERRIDE { if (match_name(old_name, id) && match_value(old_value, val, true)) { id = RTLIL::escape_id(new_name); val = make_value(new_value); @@ -112,7 +112,7 @@ struct AttrmapMap : AttrmapAction { struct AttrmapRemove : AttrmapAction { string name, value; - virtual bool apply(IdString &id, Const &val) { + bool apply(IdString &id, Const &val) YS_OVERRIDE { return !(match_name(name, id) && match_value(value, val)); } }; @@ -144,7 +144,7 @@ void attrmap_apply(string objname, vector> &actio struct AttrmapPass : public Pass { AttrmapPass() : Pass("attrmap", "renaming attributes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -179,7 +179,7 @@ struct AttrmapPass : public Pass { log(" -imap keep=\"false\" keep=0 -remove keep=0\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ATTRMAP pass (move or copy attributes).\n"); diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc index 1537def00..e59aa6518 100644 --- a/passes/techmap/attrmvcp.cc +++ b/passes/techmap/attrmvcp.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct AttrmvcpPass : public Pass { AttrmvcpPass() : Pass("attrmvcp", "move or copy attributes from wires to driving cells") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" attrmvcp [options] [selection]\n"); @@ -53,7 +53,7 @@ struct AttrmvcpPass : public Pass { log(" multiple times.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n"); diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index 0b8fd5246..9f0c7bf67 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct DeminoutPass : public Pass { DeminoutPass() : Pass("deminout", "demote inout ports to input or output") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" deminout [options] [selection]\n"); @@ -33,7 +33,7 @@ struct DeminoutPass : public Pass { log("\"Demote\" inout ports to input or output ports, if possible.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n"); diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index 4d515f174..3291f5a4a 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -253,7 +253,7 @@ struct Dff2dffeWorker struct Dff2dffePass : public Pass { Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -284,7 +284,7 @@ struct Dff2dffePass : public Pass { log(" $_DFFE_[NP]_.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n"); diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc index 0bfbdc965..39a4f6ade 100644 --- a/passes/techmap/dff2dffs.cc +++ b/passes/techmap/dff2dffs.cc @@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct Dff2dffsPass : public Pass { Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" dff2dffs [options] [selection]\n"); @@ -35,7 +35,7 @@ struct Dff2dffsPass : public Pass { log("dff2dffe for SR over CE priority.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n"); diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 6a8a86383..a8eecc970 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct DffinitPass : public Pass { DffinitPass() : Pass("dffinit", "set INIT param on FF cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -44,7 +44,7 @@ struct DffinitPass : public Pass { log(" mode.)\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n"); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 5ccb770c4..416ed2bd5 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -537,7 +537,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare struct DfflibmapPass : public Pass { DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" dfflibmap [-prepare] -liberty [selection]\n"); @@ -553,7 +553,7 @@ struct DfflibmapPass : public Pass { log("liberty file.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n"); diff --git a/passes/techmap/dffsr2dff.cc b/passes/techmap/dffsr2dff.cc index 0d4d53627..086a1d2fa 100644 --- a/passes/techmap/dffsr2dff.cc +++ b/passes/techmap/dffsr2dff.cc @@ -176,7 +176,7 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell) struct Dffsr2dffPass : public Pass { Dffsr2dffPass() : Pass("dffsr2dff", "convert DFFSR cells to simpler FF cell types") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -186,7 +186,7 @@ struct Dffsr2dffPass : public Pass { log("$_DFF_???_) to simpler FF cell types when any of the set/reset inputs is unused.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n"); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 71e29c60b..fff90f13c 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -352,7 +352,7 @@ bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right) struct ExtractPass : public Pass { ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -440,7 +440,7 @@ struct ExtractPass : public Pass { log("See 'help techmap' for a pass that does the opposite thing.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n"); log_push(); diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index af0eb852a..a8d0bc834 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -559,7 +559,7 @@ void counter_worker( struct ExtractCounterPass : public Pass { ExtractCounterPass() : Pass("extract_counter", "Extract GreenPak4 counter cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -578,7 +578,7 @@ struct ExtractCounterPass : public Pass { log("\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n"); diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index a68cc5e2e..9e6dc0d24 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -531,7 +531,7 @@ struct ExtractFaWorker struct ExtractFaPass : public Pass { ExtractFaPass() : Pass("extract_fa", "find and extract full/half adders") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -553,7 +553,7 @@ struct ExtractFaPass : public Pass { log(" Verbose output\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { ExtractFaConfig config; diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index cc21c8665..519cad55c 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -33,7 +33,7 @@ struct ExtractReducePass : public Pass ExtractReducePass() : Pass("extract_reduce", "converts gate chains into $reduce_* cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -62,7 +62,7 @@ struct ExtractReducePass : public Pass (cell->type == "$_XOR_" && gt == GateType::Xor); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing EXTRACT_REDUCE pass.\n"); log_push(); diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 82cecac26..9ec651aef 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -55,7 +55,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) struct HilomapPass : public Pass { HilomapPass() : Pass("hilomap", "technology mapping of constant hi- and/or lo-drivers") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" hilomap [options] [selection]\n"); @@ -74,7 +74,7 @@ struct HilomapPass : public Pass { log(" each constant bit.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n"); diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index aa81468dc..2173049b4 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct InsbufPass : public Pass { InsbufPass() : Pass("insbuf", "insert buffer cells for connected wires") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" insbuf [options] [selection]\n"); @@ -37,7 +37,7 @@ struct InsbufPass : public Pass { log(" call to \"clean\" will remove all $_BUF_ in the design.)\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n"); diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 690ba87ed..efcc082d5 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -34,7 +34,7 @@ void split_portname_pair(std::string &port1, std::string &port2) struct IopadmapPass : public Pass { IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" iopadmap [options] [selection]\n"); @@ -78,7 +78,7 @@ struct IopadmapPass : public Pass { log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n"); diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 2bb0bd8b4..d32bbff14 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -56,7 +56,7 @@ int lut2mux(Cell *cell) struct Lut2muxPass : public Pass { Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -65,7 +65,7 @@ struct Lut2muxPass : public Pass { log("This pass converts $lut cells to $_MUX_ gates.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n"); diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 32569d076..3e8e59e6b 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -365,7 +365,7 @@ PRIVATE_NAMESPACE_BEGIN struct MaccmapPass : public Pass { MaccmapPass() : Pass("maccmap", "mapping macc cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -375,7 +375,7 @@ struct MaccmapPass : public Pass { log("is used then the $macc cell is mapped to $add, $sub, etc. cells instead.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool unmap_mode = false; diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 1dc649587..12da9ed0c 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -561,7 +561,7 @@ struct MuxcoverWorker struct MuxcoverPass : public Pass { MuxcoverPass() : Pass("muxcover", "cover trees of MUX cells with wider MUXes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -579,7 +579,7 @@ struct MuxcoverPass : public Pass { log(" less efficient than the original circuit.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing MUXCOVER pass (mapping to wider MUXes).\n"); diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index f1a41cc3e..cc765d89c 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -129,7 +129,7 @@ struct NlutmapWorker struct NlutmapPass : public Pass { NlutmapPass() : Pass("nlutmap", "map to LUTs of different sizes") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -149,7 +149,7 @@ struct NlutmapPass : public Pass { log("to generic logic gates ($_AND_, etc.).\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { NlutmapConfig config; diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index c626dbcc5..b7a22dc3b 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -67,7 +67,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data, struct PmuxtreePass : public Pass { PmuxtreePass() : Pass("pmuxtree", "transform $pmux cells to trees of $mux cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -76,7 +76,7 @@ struct PmuxtreePass : public Pass { log("This pass transforms $pmux cells to a trees of $mux cells.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing PMUXTREE pass.\n"); diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 6936b499e..f20863ba0 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -391,7 +391,7 @@ struct ShregmapWorker struct ShregmapPass : public Pass { ShregmapPass() : Pass("shregmap", "map shift registers") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -449,7 +449,7 @@ struct ShregmapPass : public Pass { log(" map to greenpak4 shift registers.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { ShregmapOptions opts; string clkpol, enpol; diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index c6b932bdc..660b60601 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -575,7 +575,7 @@ PRIVATE_NAMESPACE_BEGIN struct SimplemapPass : public Pass { SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -590,7 +590,7 @@ struct SimplemapPass : public Pass { log(" $sr, $ff, $dff, $dffsr, $adff, $dlatch\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); extra_args(args, 1, design); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 1908ae8b5..d0e5e2236 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -891,7 +891,7 @@ struct TechmapWorker struct TechmapPass : public Pass { TechmapPass() : Pass("techmap", "generic technology mapper") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1022,7 +1022,7 @@ struct TechmapPass : public Pass { log("essentially techmap but using the design itself as map library).\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing TECHMAP pass (map to technology primitives).\n"); log_push(); @@ -1141,7 +1141,7 @@ struct TechmapPass : public Pass { struct FlattenPass : public Pass { FlattenPass() : Pass("flatten", "flatten design") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1155,7 +1155,7 @@ struct FlattenPass : public Pass { log("flattened by this command.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing FLATTEN pass (flatten design).\n"); log_push(); diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc index 03629082c..587cb9038 100644 --- a/passes/techmap/tribuf.cc +++ b/passes/techmap/tribuf.cc @@ -139,7 +139,7 @@ struct TribufWorker { struct TribufPass : public Pass { TribufPass() : Pass("tribuf", "infer tri-state buffers") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -156,7 +156,7 @@ struct TribufPass : public Pass { log(" to non-tristate logic. this option implies -merge.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { TribufConfig config; diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index a577e1235..b46147fb9 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct ZinitPass : public Pass { ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -37,7 +37,7 @@ struct ZinitPass : public Pass { log(" also add zero initialization to uninitialized FFs\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { bool all_mode = false; diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 09cb41954..5d5466afe 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -244,7 +244,7 @@ static void test_abcloop() struct TestAbcloopPass : public Pass { TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -259,7 +259,7 @@ struct TestAbcloopPass : public Pass { log(" use this value as rng seed value (default = unix time).\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design*) + void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE { int num_iter = 100; xorshift32_state = 0; diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index cb31056f4..bfb1d6642 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -324,7 +324,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s struct TestAutotbBackend : public Backend { TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -349,7 +349,7 @@ struct TestAutotbBackend : public Backend { log(" number of iterations the test bench should run (default = 1000)\n"); log("\n"); } - virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE { int num_iter = 1000; int seed = 0; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 47b6bdf23..e360b5edb 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -652,7 +652,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: struct TestCellPass : public Pass { TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -712,7 +712,7 @@ struct TestCellPass : public Pass { log(" create a Verilog test bench to test simlib and write_verilog\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design*) + void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE { int num_iter = 100; std::string techmap_cmd = "techmap -assert"; diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc index 7f4503070..92b10781d 100755 --- a/techlibs/achronix/synth_achronix.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthAchronixPass : public ScriptPass { SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -63,7 +63,7 @@ struct SynthAchronixPass : public ScriptPass { string top_opt, family_opt, vout_file; bool retime, flatten; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; vout_file = ""; @@ -71,7 +71,7 @@ struct SynthAchronixPass : public ScriptPass { flatten = true; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -118,7 +118,7 @@ struct SynthAchronixPass : public ScriptPass { log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc index cc977f97e..897f37dbb 100644 --- a/techlibs/common/prep.cc +++ b/techlibs/common/prep.cc @@ -29,7 +29,7 @@ struct PrepPass : public ScriptPass { PrepPass() : ScriptPass("prep", "generic synthesis script") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -81,7 +81,7 @@ struct PrepPass : public ScriptPass string top_module, fsm_opts; bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_module.clear(); @@ -94,7 +94,7 @@ struct PrepPass : public ScriptPass nordff = true; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; @@ -163,7 +163,7 @@ struct PrepPass : public ScriptPass log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 4ca34839e..efb214759 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -29,7 +29,7 @@ struct SynthPass : public ScriptPass { SynthPass() : ScriptPass("synth", "generic synthesis script") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -81,7 +81,7 @@ struct SynthPass : public ScriptPass string top_module, fsm_opts, memory_opts; bool autotop, flatten, noalumacc, nofsm, noabc, noshare; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_module.clear(); fsm_opts.clear(); @@ -95,7 +95,7 @@ struct SynthPass : public ScriptPass noshare = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -165,7 +165,7 @@ struct SynthPass : public ScriptPass log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc index 431e0a127..48da0d8ad 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cc +++ b/techlibs/coolrunner2/coolrunner2_sop.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Coolrunner2SopPass : public Pass { Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" coolrunner2_sop [options] [selection]\n"); @@ -33,7 +33,7 @@ struct Coolrunner2SopPass : public Pass { log("Break $sop cells into ANDTERM/ORTERM cells.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n"); extra_args(args, 1, design); diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index 2e94c3449..a5dac3566 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -29,7 +29,7 @@ struct SynthCoolrunner2Pass : public ScriptPass { SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -66,7 +66,7 @@ struct SynthCoolrunner2Pass : public ScriptPass string top_opt, json_file; bool flatten, retime; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; json_file = ""; @@ -74,7 +74,7 @@ struct SynthCoolrunner2Pass : public ScriptPass retime = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -121,7 +121,7 @@ struct SynthCoolrunner2Pass : public ScriptPass log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc index e17138f3a..b5ed93be4 100644 --- a/techlibs/easic/synth_easic.cc +++ b/techlibs/easic/synth_easic.cc @@ -29,7 +29,7 @@ struct SynthEasicPass : public ScriptPass { SynthEasicPass() : ScriptPass("synth_easic", "synthesis for eASIC platform") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -67,7 +67,7 @@ struct SynthEasicPass : public ScriptPass string top_opt, vlog_file, etools_path; bool flatten, retime; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; vlog_file = ""; @@ -76,7 +76,7 @@ struct SynthEasicPass : public ScriptPass retime = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -127,7 +127,7 @@ struct SynthEasicPass : public ScriptPass log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path.c_str()); string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path.c_str()); diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 76051d1a2..a13dd8d41 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -30,7 +30,7 @@ struct SynthEcp5Pass : public ScriptPass { SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -95,7 +95,7 @@ struct SynthEcp5Pass : public ScriptPass string top_opt, blif_file, edif_file, json_file; bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; blif_file = ""; @@ -112,7 +112,7 @@ struct SynthEcp5Pass : public ScriptPass vpr = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -199,7 +199,7 @@ struct SynthEcp5Pass : public ScriptPass log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 44dec265d..793f345be 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass { SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -61,14 +61,14 @@ struct SynthGowinPass : public ScriptPass string top_opt, vout_file; bool retime; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; vout_file = ""; retime = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -111,7 +111,7 @@ struct SynthGowinPass : public ScriptPass log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc index 7d9d7d5b0..d57e978a0 100644 --- a/techlibs/greenpak4/greenpak4_dffinv.cc +++ b/techlibs/greenpak4/greenpak4_dffinv.cc @@ -91,7 +91,7 @@ void invert_gp_dff(Cell *cell, bool invert_input) struct Greenpak4DffInvPass : public Pass { Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" greenpak4_dffinv [options] [selection]\n"); @@ -99,7 +99,7 @@ struct Greenpak4DffInvPass : public Pass { log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n"); diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 5e0e9e5d5..b91d5273a 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -29,7 +29,7 @@ struct SynthGreenPAK4Pass : public ScriptPass { SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -70,7 +70,7 @@ struct SynthGreenPAK4Pass : public ScriptPass string top_opt, part, json_file; bool flatten, retime; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; part = "SLG46621V"; @@ -79,7 +79,7 @@ struct SynthGreenPAK4Pass : public ScriptPass retime = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -133,7 +133,7 @@ struct SynthGreenPAK4Pass : public ScriptPass log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index c914b20e8..3089d8932 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Ice40FfinitPass : public Pass { Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass { log("nonzero init values.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n"); diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index 9afbc0fce..668df09dd 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Ice40FfssrPass : public Pass { Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" ice40_ffssr [options] [selection]\n"); @@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass { log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n"); diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 7af60f297..162740059 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -136,7 +136,7 @@ static void run_ice40_opts(Module *module, bool unlut_mode) struct Ice40OptPass : public Pass { Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -156,7 +156,7 @@ struct Ice40OptPass : public Pass { log("mapped SB_LUT4 cells back to logic.\n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string opt_expr_args = "-mux_undef -undriven"; bool unlut_mode = false; diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index abd890a56..b0687e5e3 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -29,7 +29,7 @@ struct SynthIce40Pass : public ScriptPass { SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -88,7 +88,7 @@ struct SynthIce40Pass : public ScriptPass string top_opt, blif_file, edif_file, json_file; bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; blif_file = ""; @@ -103,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass vpr = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -182,7 +182,7 @@ struct SynthIce40Pass : public ScriptPass log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index c51949bd4..d74f295ec 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthIntelPass : public ScriptPass { SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { } - virtual void help() YS_OVERRIDE + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass { string top_opt, family_opt, vout_file, blif_file; bool retime, flatten, nobram, noiopads; - virtual void clear_flags() YS_OVERRIDE + void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; family_opt = "max10"; @@ -91,7 +91,7 @@ struct SynthIntelPass : public ScriptPass { noiopads = false; } - virtual void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { string run_from, run_to; clear_flags(); @@ -156,7 +156,7 @@ struct SynthIntelPass : public ScriptPass { log_pop(); } - virtual void script() YS_OVERRIDE + void script() YS_OVERRIDE { if (check_label("begin")) { @@ -255,7 +255,7 @@ struct SynthIntelPass : public ScriptPass { run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s", help_mode ? "" : vout_file.c_str())); } - + if (check_label("vpr")) { if (!blif_file.empty() || help_mode) @@ -264,7 +264,7 @@ struct SynthIntelPass : public ScriptPass { run(stringf("write_blif %s", help_mode ? "" : blif_file.c_str())); } } - } + } } SynthIntelPass; PRIVATE_NAMESPACE_END diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1bc61daef..590fe61d2 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -38,7 +38,7 @@ struct SynthXilinxPass : public Pass { SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { } - virtual void help() + void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -128,7 +128,7 @@ struct SynthXilinxPass : public Pass log(" write_blif \n"); log("\n"); } - virtual void execute(std::vector args, RTLIL::Design *design) + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { std::string top_opt = "-auto-top"; std::string edif_file; From ab700ef215d7e6fd70c7b24de17f46b80de09c9f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 14:28:45 +0200 Subject: [PATCH 142/184] Add missing -lz to MXE build Signed-off-by: Clifford Wolf --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 11803ec0a..2090a083a 100644 --- a/Makefile +++ b/Makefile @@ -276,7 +276,7 @@ endif ifeq ($(CONFIG),mxe) CXXFLAGS += -DYOSYS_ENABLE_TCL -LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 +LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz else CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL ifeq ($(OS), FreeBSD) From b50fe1e3e9d2f60ebd3053d42e7f9c2f6f5a79be Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 14:35:32 +0200 Subject: [PATCH 143/184] Upodate ABC to git rev ae6716b Signed-off-by: Clifford Wolf --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 2090a083a..be266b628 100644 --- a/Makefile +++ b/Makefile @@ -107,7 +107,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = 6df1396 +ABCREV = ae6716b ABCPULL = 1 ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 From 0eaab6cd1d3fca807861a9090e684ddde16b0ba2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 15:21:59 +0200 Subject: [PATCH 144/184] Add missing include (MSVC build fix) Signed-off-by: Clifford Wolf --- passes/techmap/extract_reduce.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index cc21c8665..0ce596fda 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -19,6 +19,7 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" +#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN From e275692e84c935d0cdf42c2a4adf7ac949a88132 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 18:44:05 +0200 Subject: [PATCH 145/184] Verific: Produce errors for instantiating unknown module Because if the unknown module is connected to any constants, Verific will actually break all constants in the same module, even if they have nothing to do structurally with that instance of an unknown module. Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8937cdde8..b8dd72b98 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1800,6 +1800,9 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("db_infer_wide_operators", 1); + // WARNING: instantiating unknown module 'XYZ' (VERI-1063) + Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + verific_verbose = 0; const char *release_str = Message::ReleaseString(); From beedaa58561eb7cabf24e0d267beb77d5c78ef1d Mon Sep 17 00:00:00 2001 From: japm48 Date: Sun, 22 Jul 2018 22:29:31 +0200 Subject: [PATCH 146/184] fix basys3 example Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file to avoid warning `DRC 23-20`. Added `open_hw` needed for programming. --- examples/basys3/example.xdc | 3 +++ examples/basys3/run_prog.tcl | 1 + 2 files changed, 4 insertions(+) diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc index c1fd0e925..8cdaa1996 100644 --- a/examples/basys3/example.xdc +++ b/examples/basys3/example.xdc @@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + diff --git a/examples/basys3/run_prog.tcl b/examples/basys3/run_prog.tcl index d711af840..b078ad511 100644 --- a/examples/basys3/run_prog.tcl +++ b/examples/basys3/run_prog.tcl @@ -1,3 +1,4 @@ +open_hw connect_hw_server open_hw_target [lindex [get_hw_targets] 0] set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0] From f42d6a9c93f8bd456bf5e857dc67f19e3b10ab25 Mon Sep 17 00:00:00 2001 From: litghost <537074+litghost@users.noreply.github.com> Date: Thu, 2 Aug 2018 14:33:39 -0700 Subject: [PATCH 147/184] Add BLIF parsing support for .conn and .cname --- frontends/blif/blifparse.cc | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index e6bb99954..e2be61da8 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -83,6 +83,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo RTLIL::Module *module = nullptr; RTLIL::Const *lutptr = NULL; RTLIL::Cell *sopcell = NULL; + RTLIL::Cell *lastcell = nullptr; RTLIL::State lut_default_state = RTLIL::State::Sx; int blif_maxnum = 0, sopmode = -1; @@ -159,6 +160,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo if (module != nullptr) goto error; module = new RTLIL::Module; + lastcell = nullptr; module->name = RTLIL::escape_id(strtok(NULL, " \t\r\n")); obj_attributes = &module->attributes; obj_parameters = nullptr; @@ -232,6 +234,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo } module = nullptr; + lastcell = nullptr; obj_attributes = nullptr; obj_parameters = nullptr; continue; @@ -264,6 +267,22 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo continue; } + if (!strcmp(cmd, ".cname")) + { + char *p = strtok(NULL, " \t\r\n"); + if (p == NULL) + goto error; + + if(lastcell == nullptr || module == nullptr) + { + log_error("No primative object to attach .cname %s.\n", p); + goto error; + } + + module->rename(lastcell, p); + continue; + } + if (!strcmp(cmd, ".attr") || !strcmp(cmd, ".param")) { char *n = strtok(NULL, " \t\r\n"); char *v = strtok(NULL, "\r\n"); @@ -281,12 +300,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0; } if (!strcmp(cmd, ".attr")) { - if (obj_attributes == nullptr) + if (obj_attributes == nullptr) { + log_error("No object to attach .attr too.\n"); goto error; + } (*obj_attributes)[id_n] = const_v; } else { - if (obj_parameters == nullptr) + if (obj_parameters == nullptr) { + log_error("No object to attach .param too.\n"); goto error; + } (*obj_parameters)[id_n] = const_v; } continue; @@ -331,6 +354,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo } } + lastcell = cell; obj_attributes = &cell->attributes; obj_parameters = &cell->parameters; continue; @@ -383,6 +407,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo cell->setPort(it.first, sig); } + lastcell = cell; obj_attributes = &cell->attributes; obj_parameters = &cell->parameters; continue; @@ -391,7 +416,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo obj_attributes = nullptr; obj_parameters = nullptr; - if (!strcmp(cmd, ".barbuf")) + if (!strcmp(cmd, ".barbuf") || !strcmp(cmd, ".conn")) { char *p = strtok(NULL, " \t\r\n"); if (p == NULL) @@ -459,6 +484,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo sopcell->setPort("\\A", input_sig); sopcell->setPort("\\Y", output_sig); sopmode = -1; + lastcell = sopcell; } else { @@ -469,6 +495,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo cell->setPort("\\Y", output_sig); lutptr = &cell->parameters.at("\\LUT"); lut_default_state = RTLIL::State::Sx; + lastcell = cell; } continue; } From 475c2af8120199f0acaa02e6e0993b27a553b22f Mon Sep 17 00:00:00 2001 From: litghost <537074+litghost@users.noreply.github.com> Date: Fri, 3 Aug 2018 08:02:49 -0700 Subject: [PATCH 148/184] Use log_warning which does not immediately terminate. --- frontends/blif/blifparse.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index e2be61da8..1d4cf39a8 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -275,7 +275,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo if(lastcell == nullptr || module == nullptr) { - log_error("No primative object to attach .cname %s.\n", p); + log_warning("No primative object to attach .cname %s.\n", p); goto error; } @@ -301,13 +301,13 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo } if (!strcmp(cmd, ".attr")) { if (obj_attributes == nullptr) { - log_error("No object to attach .attr too.\n"); + log_warning("No object to attach .attr too.\n"); goto error; } (*obj_attributes)[id_n] = const_v; } else { if (obj_parameters == nullptr) { - log_error("No object to attach .param too.\n"); + log_warning("No object to attach .param too.\n"); goto error; } (*obj_parameters)[id_n] = const_v; From da53206cd4b1e32d8bf29bb33cdfec81d614525e Mon Sep 17 00:00:00 2001 From: Konrad Beckmann Date: Mon, 6 Aug 2018 13:30:33 +0900 Subject: [PATCH 149/184] readme: Fix formatting of a keyword Single quotes were used instead of backticks leading to incorrect formatting. --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c02691d94..424d9bbf2 100644 --- a/README.md +++ b/README.md @@ -389,7 +389,7 @@ Verilog Attributes and non-standard features Non-standard or SystemVerilog features for formal verification ============================================================== -- Support for ``assert``, ``assume``, ``restrict``, and ``cover'' is enabled +- Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled when ``read_verilog`` is called with ``-formal``. - The system task ``$initstate`` evaluates to 1 in the initial state and From 7db05b2cc1befba7e9d7afbb270dd503e8ec5857 Mon Sep 17 00:00:00 2001 From: jpathy <15735913+jpathy@users.noreply.github.com> Date: Mon, 6 Aug 2018 06:51:07 +0000 Subject: [PATCH 150/184] Use `realpath` Use `os.path.realpath` instead to make sure symlinks are followed. This is also required to work for nix package manager. --- backends/smt2/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/smt2/Makefile.inc b/backends/smt2/Makefile.inc index eacda2734..dce82f01a 100644 --- a/backends/smt2/Makefile.inc +++ b/backends/smt2/Makefile.inc @@ -6,7 +6,7 @@ ifneq ($(CONFIG),emcc) TARGETS += yosys-smtbmc yosys-smtbmc: backends/smt2/smtbmc.py - $(P) sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(__file__) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < $< > $@.new + $(P) sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < $< > $@.new $(Q) chmod +x $@.new $(Q) mv $@.new $@ From 219f1e9fc9bda90422d1ec81db581a0f469ef192 Mon Sep 17 00:00:00 2001 From: litghost <537074+litghost@users.noreply.github.com> Date: Wed, 8 Aug 2018 10:22:55 -0700 Subject: [PATCH 151/184] Report error reason on same line as syntax error. Signed-off-by: litghost <537074+litghost@users.noreply.github.com> --- frontends/blif/blifparse.cc | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 1d4cf39a8..b81808b1e 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -85,6 +85,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo RTLIL::Cell *sopcell = NULL; RTLIL::Cell *lastcell = nullptr; RTLIL::State lut_default_state = RTLIL::State::Sx; + char err_reason[80]; int blif_maxnum = 0, sopmode = -1; auto blif_wire = [&](const std::string &wire_name) -> Wire* @@ -275,8 +276,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo if(lastcell == nullptr || module == nullptr) { - log_warning("No primative object to attach .cname %s.\n", p); - goto error; + snprintf(err_reason, sizeof(err_reason), "No primative object to attach .cname %s.", p); + goto error_with_reason; } module->rename(lastcell, p); @@ -301,14 +302,14 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo } if (!strcmp(cmd, ".attr")) { if (obj_attributes == nullptr) { - log_warning("No object to attach .attr too.\n"); - goto error; + snprintf(err_reason, sizeof(err_reason), "No object to attach .attr too."); + goto error_with_reason; } (*obj_attributes)[id_n] = const_v; } else { if (obj_parameters == nullptr) { - log_warning("No object to attach .param too.\n"); - goto error; + snprintf(err_reason, sizeof(err_reason), "No object to attach .param too."); + goto error_with_reason; } (*obj_parameters)[id_n] = const_v; } @@ -573,6 +574,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo error: log_error("Syntax error in line %d!\n", line_count); +error_with_reason: + log_error("Syntax error in line %d: %s\n", line_count, err_reason); } struct BlifFrontend : public Frontend { From 93efbd5d158e374a0abe2afb06484ccc14aa2c88 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 8 Aug 2018 19:41:47 +0200 Subject: [PATCH 152/184] Fixed use of char array for string in blifparse error handling Signed-off-by: Clifford Wolf --- frontends/blif/blifparse.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index b81808b1e..26cd14033 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -85,7 +85,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo RTLIL::Cell *sopcell = NULL; RTLIL::Cell *lastcell = nullptr; RTLIL::State lut_default_state = RTLIL::State::Sx; - char err_reason[80]; + std::string err_reason; int blif_maxnum = 0, sopmode = -1; auto blif_wire = [&](const std::string &wire_name) -> Wire* @@ -276,7 +276,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo if(lastcell == nullptr || module == nullptr) { - snprintf(err_reason, sizeof(err_reason), "No primative object to attach .cname %s.", p); + err_reason = stringf("No primative object to attach .cname %s.", p); goto error_with_reason; } @@ -302,13 +302,13 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo } if (!strcmp(cmd, ".attr")) { if (obj_attributes == nullptr) { - snprintf(err_reason, sizeof(err_reason), "No object to attach .attr too."); + err_reason = stringf("No object to attach .attr too."); goto error_with_reason; } (*obj_attributes)[id_n] = const_v; } else { if (obj_parameters == nullptr) { - snprintf(err_reason, sizeof(err_reason), "No object to attach .param too."); + err_reason = stringf("No object to attach .param too."); goto error_with_reason; } (*obj_parameters)[id_n] = const_v; @@ -575,7 +575,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo error: log_error("Syntax error in line %d!\n", line_count); error_with_reason: - log_error("Syntax error in line %d: %s\n", line_count, err_reason); + log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str()); } struct BlifFrontend : public Frontend { From 80d7e007ff4cbe0a9669224751c68e5325fbed0a Mon Sep 17 00:00:00 2001 From: litghost <537074+litghost@users.noreply.github.com> Date: Mon, 13 Aug 2018 14:02:53 -0700 Subject: [PATCH 153/184] Map .eblif extension as blif. Signed-off-by: litghost <537074+litghost@users.noreply.github.com> --- kernel/yosys.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 750a154e6..dca277532 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -825,6 +825,8 @@ void run_frontend(std::string filename, std::string command, std::string *backen command = "vhdl"; else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif") command = "blif"; + else if (filename.size() > 5 && filename.substr(filename.size()-6) == ".eblif") + command = "blif"; else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".json") command = "json"; else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") From 1dd156f5167d9949eccb7abcbc65d9bc74f49ee8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 14 Aug 2018 23:31:25 +0200 Subject: [PATCH 154/184] Fix use of signed integers in JSON back-end Signed-off-by: Clifford Wolf --- backends/json/json.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/backends/json/json.cc b/backends/json/json.cc index d3b7077a2..1a3ca64a3 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -93,8 +93,10 @@ struct JsonWriter f << get_string(param.second.decode_string()); else if (GetSize(param.second.bits) > 32) f << get_string(param.second.as_string()); - else + else if ((param.second.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) != 0) f << stringf("%d", param.second.as_int()); + else + f << stringf("%u", param.second.as_int()); first = false; } } From a5136c768b87c3e7ad675888ec51dbe3fc030fc2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 15 Aug 2018 19:08:45 +0200 Subject: [PATCH 155/184] Changes for MXE configuration in order to compile --- Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index c90ff6da9..eed4e8f23 100644 --- a/Makefile +++ b/Makefile @@ -200,14 +200,14 @@ yosys.html: misc/yosys.html else ifeq ($(CONFIG),mxe) PKG_CONFIG = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-pkg-config -CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc -LD = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc +CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++ +LD = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++ CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDLIBS := $(filter-out -lrt,$(LDLIBS)) -ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" -ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 +ABCMKARGS += ARCHFLAGS="-DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" +ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc" EXE = .exe else ifeq ($(CONFIG),msys2) From 28cfc75a902574c3ad96876d2f5e01af6c583bac Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Wed, 15 Aug 2018 19:56:30 +0300 Subject: [PATCH 156/184] A few minor enhancements to specify block parsing. Just remember specify blocks are parsed but ignored. --- frontends/verilog/verilog_parser.y | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 78cac5543..61da12b76 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -688,8 +688,8 @@ path_declaration : ; simple_path_declaration : - parallel_path_description '=' path_delay_value ';' - // | full_path_description '=' path_delay_value ';' + parallel_path_description '=' path_delay_value ';' | + full_path_description '=' path_delay_value ';' ; path_delay_value : @@ -723,6 +723,17 @@ list_of_path_delay_expressions : parallel_path_description : '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; +full_path_description : + '(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ; + +list_of_path_inputs : + specify_input_terminal_descriptor | + list_of_path_inputs ',' specify_input_terminal_descriptor ; + +list_of_path_outputs : + specify_output_terminal_descriptor | + list_of_path_outputs ',' specify_output_terminal_descriptor ; + opt_polarity_operator : '+' | '-' From 9f91c62348c533d0d0d167a393bab284b2c6de8d Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Wed, 15 Aug 2018 17:15:44 -0400 Subject: [PATCH 157/184] Fix run_command() when using -format and -viewer in show pass. --- passes/cmds/show.cc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index ec04418fa..fa88cd668 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -817,14 +817,30 @@ struct ShowPass : public Pass { log_cmd_error("Nothing there to show.\n"); if (format != "dot" && !format.empty()) { - std::string cmd = stringf("dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'", format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str()); + #ifdef _WIN32 + // system()/cmd.exe does not understand single quotes on Windows. + #define DOT_CMD "dot -T%s \"%s\" > \"%s.new\" && move \"%s.new\" \"%s\"" + #else + #define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'" + #endif + std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str()); + #undef DOT_CMD log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); } if (!viewer_exe.empty()) { - std::string cmd = stringf("%s '%s' &", viewer_exe.c_str(), out_file.c_str()); + #ifdef _WIN32 + // system()/cmd.exe does not understand single quotes nor + // background tasks on Windows. So we have to pause yosys + // until the viewer exits. + #define VIEW_CMD "%s \"%s\"" + #else + #define VIEW_CMD "%s '%s' &" + #endif + std::string cmd = stringf(VIEW_CMD, viewer_exe.c_str(), out_file.c_str()); + #undef VIEW_CMD log("Exec: %s\n", cmd.c_str()); if (run_command(cmd) != 0) log_cmd_error("Shell command failed!\n"); From 7ce7ea2eb4903058ac4560d7b192cb5ed02aed89 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Wed, 15 Aug 2018 17:16:07 -0400 Subject: [PATCH 158/184] Update show pass documentation with Windows caveats. --- passes/cmds/show.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index fa88cd668..a48873244 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -584,6 +584,7 @@ struct ShowPass : public Pass { log("\n"); log(" -viewer \n"); log(" Run the specified command with the graphics file as parameter.\n"); + log(" On Windows, this pauses yosys until the viewer exits.\n"); log("\n"); log(" -format \n"); log(" Generate a graphics file in the specified format. Use 'dot' to just\n"); @@ -645,7 +646,7 @@ struct ShowPass : public Pass { log(" do not add the module name as graph title to the dot file\n"); log("\n"); log("When no is specified, 'dot' is used. When no and is\n"); - log("specified, 'xdot' is used to display the schematic.\n"); + log("specified, 'xdot' is used to display the schematic (POSIX systems only).\n"); log("\n"); log("The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.',\n"); log("unless another prefix is specified using -prefix .\n"); From 0899a53bee39e209551a3122c7c820b7ed2b48c3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 16 Aug 2018 11:31:19 +0200 Subject: [PATCH 159/184] Verific workaround for VIPER ticket 13851 Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index e993eb740..2895d40c2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1800,6 +1800,9 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("db_infer_wide_operators", 1); + // Workaround for VIPER #13851 + RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); + // WARNING: instantiating unknown module 'XYZ' (VERI-1063) Message::SetMessageType("VERI-1063", VERIFIC_ERROR); From e343f3e6d475984c21611474bffe7dcd8f599497 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 16 Aug 2018 11:49:17 +0200 Subject: [PATCH 160/184] Add "verific -set- .." Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 62 +++++++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 12 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 2895d40c2..b8c0375ce 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1732,6 +1732,15 @@ struct VerificPass : public Pass { log("Remove Verilog defines previously set with -vlog-define.\n"); log("\n"); log("\n"); + log(" verific -set-error ..\n"); + log(" verific -set-warning ..\n"); + log(" verific -set-info ..\n"); + log(" verific -set-ignore ..\n"); + log("\n"); + log("Set message severity. is the string in square brackets when a message\n"); + log("is printed, such as VERI-1209.\n"); + log("\n"); + log("\n"); log(" verific -import [options] ..\n"); log("\n"); log("Elaborate the design for the specified top modules, import to Yosys and\n"); @@ -1786,25 +1795,32 @@ struct VerificPass : public Pass { #ifdef YOSYS_ENABLE_VERIFIC void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + static bool set_verific_global_flags = true; + if (check_noverific_env()) log_cmd_error("This version of Yosys is built without Verific support.\n"); log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n"); - Message::SetConsoleOutput(0); - Message::RegisterCallBackMsg(msg_func); - RuntimeFlags::SetVar("db_preserve_user_nets", 1); - RuntimeFlags::SetVar("db_allow_external_nets", 1); - RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); - RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); - RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); - RuntimeFlags::SetVar("db_infer_wide_operators", 1); + if (set_verific_global_flags) + { + Message::SetConsoleOutput(0); + Message::RegisterCallBackMsg(msg_func); + RuntimeFlags::SetVar("db_preserve_user_nets", 1); + RuntimeFlags::SetVar("db_allow_external_nets", 1); + RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); + RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); + RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); + RuntimeFlags::SetVar("db_infer_wide_operators", 1); - // Workaround for VIPER #13851 - RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); + // Workaround for VIPER #13851 + RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); - // WARNING: instantiating unknown module 'XYZ' (VERI-1063) - Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + // WARNING: instantiating unknown module 'XYZ' (VERI-1063) + Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + + set_verific_global_flags = false; + } verific_verbose = 0; @@ -1822,6 +1838,28 @@ struct VerificPass : public Pass { int argidx = 1; + if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" || + args[argidx] == "-set-info" || args[argidx] == "-set-ignore")) + { + msg_type_t new_type; + + if (args[argidx] == "-set-error") + new_type = VERIFIC_ERROR; + else if (args[argidx] == "-set-warning") + new_type = VERIFIC_WARNING; + else if (args[argidx] == "-set-info") + new_type = VERIFIC_INFO; + else if (args[argidx] == "-set-ignore") + new_type = VERIFIC_IGNORE; + else + log_abort(); + + for (argidx++; argidx < GetSize(args); argidx++) + Message::SetMessageType(args[argidx].c_str(), new_type); + + goto check_error; + } + if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") { for (argidx++; argidx < GetSize(args); argidx++) verific_incdirs.push_back(args[argidx]); From 83b41260f6c8dd3ba617cc03b06435521038e7db Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Sat, 18 Aug 2018 09:08:07 +0530 Subject: [PATCH 161/184] Revision to expose option in setundef pass Corrects indentation Simplifications and corrections --- passes/cmds/setundef.cc | 247 ++++++++++++++++++---------------------- 1 file changed, 108 insertions(+), 139 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index eac1f6236..62d940ce6 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -33,67 +33,32 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global) +static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output) { - RTLIL::Wire *wire = NULL; - name = RTLIL::escape_id(name); + RTLIL::Wire *wire = NULL; + name = RTLIL::escape_id(name); - if (module->count_id(name) != 0) - { - if (module->wires_.count(name) > 0) - wire = module->wires_.at(name); + if (module->count_id(name) != 0) + { + log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str()); + name += "$"; + return add_wire(module, name, width, flag_input, flag_output); + } + else + { + wire = module->addWire(name, width); + wire->port_input = flag_input; + wire->port_output = flag_output; - if (wire != NULL && wire->width != width) - wire = NULL; + if (flag_input || flag_output) { + wire->port_id = module->wires_.size(); + module->fixup_ports(); + } - if (wire != NULL && wire->port_input != flag_input) - wire = NULL; + log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); + } - if (wire != NULL && wire->port_output != flag_output) - wire = NULL; - - if (wire == NULL) { - return wire; - log_cmd_error("Found incompatible object %s with same name in module %s!\n", name.c_str(), module->name.c_str()); - } - - log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str()); - } - else - { - wire = module->addWire(name, width); - wire->port_input = flag_input; - wire->port_output = flag_output; - - if (flag_input || flag_output) { - wire->port_id = module->wires_.size(); - module->fixup_ports(); - } - - log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str()); - } - - if (!flag_global) - return wire; - - for (auto &it : module->cells_) - { - if (design->modules_.count(it.second->type) == 0) - continue; - - RTLIL::Module *mod = design->modules_.at(it.second->type); - if (!design->selected_whole_module(mod->name)) - continue; - if (mod->get_bool_attribute("\\blackbox")) - continue; - if (it.second->hasPort(name)) - continue; - - it.second->setPort(name, wire); - log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); - } - - return wire; + return wire; } struct SetundefWorker @@ -262,100 +227,104 @@ struct SetundefPass : public Pass { if (!module->processes.empty()) log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n"); - if (expose_mode) { - SigMap sigmap(module); - dict wire_drivers; - pool used_wires; - SigPool undriven_signals; + if (expose_mode) + { + SigMap sigmap(module); + dict wire_drivers; + pool used_wires; + SigPool undriven_signals; - for (auto cell : module->cells()) - for (auto &conn : cell->connections()) { - SigSpec sig = sigmap(conn.second); - if (cell->input(conn.first)) - for (auto bit : sig) - if (bit.wire) { - used_wires.insert(bit); - } - if (cell->output(conn.first)) - for (int i = 0; i < GetSize(sig); i++) { - if (sig[i].wire) - wire_drivers[sig[i]] = true; - } - } + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) { + SigSpec sig = sigmap(conn.second); + if (cell->input(conn.first)) + for (auto bit : sig) + if (bit.wire) + used_wires.insert(bit); + if (cell->output(conn.first)) + for (int i = 0; i < GetSize(sig); i++) + if (sig[i].wire) + wire_drivers[sig[i]] = true; + } - for (auto wire : module->wires()) { - if (wire->port_input) { - SigSpec sig = sigmap(wire); - for (int i = 0; i < GetSize(sig); i++) - wire_drivers[sig[i]] = true; - } - if (wire->port_output) - for (auto bit : sigmap(wire)) - if (bit.wire) used_wires.insert(bit); - } + for (auto wire : module->wires()) { + if (wire->port_input) { + SigSpec sig = sigmap(wire); + for (int i = 0; i < GetSize(sig); i++) + wire_drivers[sig[i]] = true; + } + if (wire->port_output) { + SigSpec sig = sigmap(wire); + for (auto bit : sig) + if (bit.wire) + used_wires.insert(bit); + } + } - pool undriven_wires; - for (auto bit : used_wires) { - if (!wire_drivers.count(bit)) { - undriven_wires.insert(bit.wire); - } - } + pool undriven_wires; + for (auto bit : used_wires) + if (!wire_drivers.count(bit)) + undriven_wires.insert(bit.wire); - for (auto &it : undriven_wires) - undriven_signals.add(sigmap(it)); + for (auto &it : undriven_wires) + undriven_signals.add(sigmap(it)); - for (auto &it : undriven_wires) - if (it->port_input) - undriven_signals.del(sigmap(it)); + for (auto &it : undriven_wires) + if (it->port_input) + undriven_signals.del(sigmap(it)); - CellTypes ct(design); - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) - undriven_signals.del(sigmap(conn.second)); + CellTypes ct(design); + for (auto &it : module->cells_) + for (auto &conn : it.second->connections()) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); - RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks()) { - RTLIL::Wire * wire; - if (c.wire->width == c.width) { - wire = c.wire; - wire->port_input = true; - } - else { - string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; - wire = add_wire(design, module, name, c.width, true, false, false); - module->connect(RTLIL::SigSig(c, wire)); - } - log("Exposing undriven wire %s as input.\n", wire->name.c_str()); - } - module->fixup_ports(); - continue; - } - else { - SigMap sigmap(module); - SigPool undriven_signals; + RTLIL::SigSpec sig = undriven_signals.export_all(); + for (auto &c : sig.chunks()) { + RTLIL::Wire * wire; + if (c.wire->width == c.width) { + wire = c.wire; + wire->port_input = true; + } else { + string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]"; + wire = add_wire(module, name, c.width, true, false); + module->connect(RTLIL::SigSig(c, wire)); + } + log("Exposing undriven wire %s as input.\n", wire->name.c_str()); + } + module->fixup_ports(); + } + else + { + SigMap sigmap(module); + SigPool undriven_signals; - for (auto &it : module->wires_) - undriven_signals.add(sigmap(it.second)); + for (auto &it : module->wires_) + undriven_signals.add(sigmap(it.second)); - for (auto &it : module->wires_) - if (it.second->port_input) - undriven_signals.del(sigmap(it.second)); + for (auto &it : module->wires_) + if (it.second->port_input) + undriven_signals.del(sigmap(it.second)); - CellTypes ct(design); - for (auto &it : module->cells_) - for (auto &conn : it.second->connections()) - if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) - undriven_signals.del(sigmap(conn.second)); + CellTypes ct(design); + for (auto &it : module->cells_) + for (auto &conn : it.second->connections()) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); - RTLIL::SigSpec sig = undriven_signals.export_all(); - for (auto &c : sig.chunks()) { - RTLIL::SigSpec bits; - for (int i = 0; i < c.width; i++) - bits.append(worker.next_bit()); - module->connect(RTLIL::SigSig(c, bits)); - } - } + RTLIL::SigSpec sig = undriven_signals.export_all(); + for (auto &c : sig.chunks()) { + RTLIL::SigSpec bits; + if (worker.next_bit_mode == MODE_ANYSEQ) + bits = module->Anyseq(NEW_ID, c.width); + else if (worker.next_bit_mode == MODE_ANYCONST) + bits = module->Anyconst(NEW_ID, c.width); + else + for (int i = 0; i < c.width; i++) + bits.append(worker.next_bit()); + module->connect(RTLIL::SigSig(c, bits)); + } + } } if (init_mode) From 3e20788c24d2b0472fa9e3ecee31b636c5866d8d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 18 Aug 2018 14:00:55 +0200 Subject: [PATCH 162/184] Added gcc-static for easier cross compilation --- Makefile | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index eed4e8f23..c2a3293ae 100644 --- a/Makefile +++ b/Makefile @@ -156,6 +156,14 @@ LD = gcc CXXFLAGS += -std=c++11 -Os ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" +else ifeq ($(CONFIG),gcc-static) +LD = $(CXX) +LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s +LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) +CXXFLAGS += -std=c++11 -Os +ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \ + ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1 + else ifeq ($(CONFIG),gcc-4.8) CXX = gcc-4.8 LD = gcc-4.8 @@ -671,6 +679,12 @@ config-clang: clean config-gcc: clean echo 'CONFIG := gcc' > Makefile.conf +config-gcc-static: clean + echo 'CONFIG := gcc-static' > Makefile.conf + echo 'ENABLE_PLUGINS := 0' >> Makefile.conf + echo 'ENABLE_READLINE := 0' >> Makefile.conf + echo 'ENABLE_TCL := 0' >> Makefile.conf + config-gcc-4.8: clean echo 'CONFIG := gcc-4.8' > Makefile.conf @@ -712,5 +726,5 @@ echo-git-rev: -include techlibs/*/*.d .PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator -.PHONY: config-clean config-clang config-gcc config-gcc-4.8 config-gprof config-sudo +.PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo From 539053ab68d7a124f0c710e3fbd87aba8ee8b0aa Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 18 Aug 2018 14:14:17 +0200 Subject: [PATCH 163/184] Added option to disable -fPIC on unsupported platforms --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index c2a3293ae..c2a076229 100644 --- a/Makefile +++ b/Makefile @@ -160,6 +160,9 @@ else ifeq ($(CONFIG),gcc-static) LD = $(CXX) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) +ifeq ($(NO_FPIC),1) +CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) +endif CXXFLAGS += -std=c++11 -Os ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \ ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1 From 45740236b6b0aa8d445fb3fea8d8c1ec497be3cf Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 18 Aug 2018 15:11:58 +0200 Subject: [PATCH 164/184] Enable propagating ARCHFLAGS --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index c2a076229..024b216f0 100644 --- a/Makefile +++ b/Makefile @@ -164,8 +164,8 @@ ifeq ($(NO_FPIC),1) CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) endif CXXFLAGS += -std=c++11 -Os -ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \ - ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1 +ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-static -lm -lpthread" OPTFLAGS="-O" \ + ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1 else ifeq ($(CONFIG),gcc-4.8) CXX = gcc-4.8 From 443865ab870248aed91700686160d36ed616503d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 18 Aug 2018 18:21:28 +0200 Subject: [PATCH 165/184] respect DISABLE_ABC_THREADS if used --- Makefile | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 024b216f0..c3e3a4b47 100644 --- a/Makefile +++ b/Makefile @@ -159,13 +159,16 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" else ifeq ($(CONFIG),gcc-static) LD = $(CXX) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s -LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) +LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) ifeq ($(NO_FPIC),1) CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) endif CXXFLAGS += -std=c++11 -Os -ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-static -lm -lpthread" OPTFLAGS="-O" \ +ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \ ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1 +ifeq ($(DISABLE_ABC_THREADS),1) +ABCMKARGS += "ABC_USE_NO_PTHREADS=1" +endif else ifeq ($(CONFIG),gcc-4.8) CXX = gcc-4.8 From 75d185294362ae9ed2fbb08e5348cbdf113c3e8f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 18 Aug 2018 19:17:02 +0200 Subject: [PATCH 166/184] no -fPIC for any static build --- Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Makefile b/Makefile index c3e3a4b47..c1e5c789d 100644 --- a/Makefile +++ b/Makefile @@ -159,10 +159,8 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" else ifeq ($(CONFIG),gcc-static) LD = $(CXX) LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s -LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) -ifeq ($(NO_FPIC),1) +LDLIBS := $(filter-out -lrt,$(LDLIBS)) CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) -endif CXXFLAGS += -std=c++11 -Os ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \ ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1 From 95241c8f4d32c5bd644bef71509965a82582264c Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Mon, 20 Aug 2018 00:08:08 +0300 Subject: [PATCH 167/184] Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value. --- frontends/verilog/verilog_parser.y | 32 ++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 61da12b76..58a6824d1 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -654,7 +654,7 @@ specify_item: // | pulsestyle_declaration // | showcancelled_declaration | path_declaration - // | system_timing_declaration + | system_timing_declaration ; specparam_declaration: @@ -693,8 +693,8 @@ simple_path_declaration : ; path_delay_value : - //list_of_path_delay_expressions - '(' list_of_path_delay_expressions ')' + list_of_path_delay_expressions | + %prec '(' list_of_path_delay_expressions ')' ; list_of_path_delay_expressions : @@ -724,12 +724,17 @@ parallel_path_description : '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; full_path_description : - '(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ; + '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ; +// This was broken into 2 rules to solve shift/reduce conflicts list_of_path_inputs : - specify_input_terminal_descriptor | - list_of_path_inputs ',' specify_input_terminal_descriptor ; - + specify_input_terminal_descriptor opt_polarity_operator | + specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ; + +more_path_inputs : + ',' specify_input_terminal_descriptor | + more_path_inputs ',' specify_input_terminal_descriptor ; + list_of_path_outputs : specify_output_terminal_descriptor | list_of_path_outputs ',' specify_output_terminal_descriptor ; @@ -747,11 +752,18 @@ specify_input_terminal_descriptor : specify_output_terminal_descriptor : TOK_ID ; -/* system_timing_declaration : - ; -*/ + TOK_ID '(' system_timing_args ')' ';' ; +system_timing_arg : + TOK_POSEDGE TOK_ID | + TOK_NEGEDGE TOK_ID | + expr ; + +system_timing_args : + system_timing_arg | + system_timing_args ',' system_timing_arg ; + /* t_path_delay_expression : path_delay_expression; From fbfc677df3e54798faba3ab2f27c270759b96507 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Mon, 20 Aug 2018 17:27:45 +0300 Subject: [PATCH 168/184] Fixed all known specify/endspecify issues, without breaking 'make test'. Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses --- frontends/verilog/verilog_parser.y | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 58a6824d1..2389d7d31 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -682,22 +682,23 @@ showcancelled_declaration : */ path_declaration : - simple_path_declaration + simple_path_declaration ';' // | edge_sensitive_path_declaration // | state_dependent_path_declaration ; simple_path_declaration : - parallel_path_description '=' path_delay_value ';' | - full_path_description '=' path_delay_value ';' + parallel_path_description '=' path_delay_value | + full_path_description '=' path_delay_value ; path_delay_value : - list_of_path_delay_expressions | - %prec '(' list_of_path_delay_expressions ')' + '(' path_delay_expression list_of_path_delay_extra_expressions ')' + | path_delay_expression + | path_delay_expression list_of_path_delay_extra_expressions ; -list_of_path_delay_expressions : +list_of_path_delay_extra_expressions : /* t_path_delay_expression | trise_path_delay_expression ',' tfall_path_delay_expression @@ -709,12 +710,11 @@ list_of_path_delay_expressions : t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ',' tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression */ - path_delay_expression - | path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + ',' path_delay_expression + | ',' path_delay_expression ',' path_delay_expression + | ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression - | path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' + | ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression @@ -815,7 +815,7 @@ tzx_path_delay_expression : */ path_delay_expression : - constant_mintypmax_expression; + constant_expression; constant_mintypmax_expression : constant_expression From 4b02ee91627c49bd4ea0e89d6c8531283501a24b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 22 Aug 2018 13:30:22 +0200 Subject: [PATCH 169/184] Add Verific -work parameter Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b8c0375ce..cb31634dd 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1837,6 +1837,7 @@ struct VerificPass : public Pass { log("Built with Verific %s, released at %s.\n", release_str, release_tmstr); int argidx = 1; + std::string work = "work"; if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" || args[argidx] == "-set-info" || args[argidx] == "-set-ignore")) @@ -1895,6 +1896,15 @@ struct VerificPass : public Pass { goto check_error; } + for (; argidx < GetSize(args); argidx++) + { + if (args[argidx] == "-work" && argidx+1 < GetSize(args)) { + work = args[++argidx]; + continue; + } + break; + } + if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" || args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal")) { @@ -1942,7 +1952,7 @@ struct VerificPass : public Pass { while (argidx < GetSize(args)) file_names.Insert(args[argidx++].c_str()); - if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU)) + if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); verific_import_pending = true; @@ -1952,7 +1962,7 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && args[argidx] == "-vhdl87") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str()); for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87)) + if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87)) log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str()); verific_import_pending = true; goto check_error; @@ -1961,7 +1971,7 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && args[argidx] == "-vhdl93") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93)) + if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93)) log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str()); verific_import_pending = true; goto check_error; @@ -1970,7 +1980,7 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K)) + if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K)) log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str()); verific_import_pending = true; goto check_error; @@ -1979,7 +1989,7 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008)) + if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008)) log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str()); verific_import_pending = true; goto check_error; @@ -2089,8 +2099,8 @@ struct VerificPass : public Pass { #else log("Running hier_tree::ElaborateAll().\n"); - VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); - VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1); + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); + VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); Array veri_libs, vhdl_libs; if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); @@ -2137,7 +2147,7 @@ struct VerificPass : public Pass { continue; } - VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(name); if (vhdl_unit) { log("Adding VHDL unit '%s' to elaboration queue.\n", name); From 408077769ff022f78f10ec1ffb60926361f8dc9f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 22 Aug 2018 17:22:24 +0200 Subject: [PATCH 170/184] Add "verific -work" help message Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index cb31634dd..1dd6d7e24 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1706,11 +1706,18 @@ struct VerificPass : public Pass { log("\n"); log("Like -sv, but define FORMAL instead of SYNTHESIS.\n"); log("\n"); + log("\n"); log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} ..\n"); log("\n"); log("Load the specified VHDL files into Verific.\n"); log("\n"); log("\n"); + log(" verific -work {-sv|-vhdl|...} \n"); + log("\n"); + log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n"); + log("(default library when -work is not present: \"work\")\n"); + log("\n"); + log("\n"); log(" verific -vlog-incdir ..\n"); log("\n"); log("Add Verilog include directories.\n"); From 042b3074f8096212b3f2114d353b2ec75818810b Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Thu, 23 Aug 2018 15:19:46 +0300 Subject: [PATCH 171/184] Added -no_dump_ptr flag for AST dump options in 'read_verilog' This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. --- frontends/ast/ast.cc | 15 +++++++++------ frontends/ast/ast.h | 4 ++-- frontends/verilog/verilog_frontend.cc | 10 +++++++++- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 7c72a50d9..e79be953a 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -44,7 +44,7 @@ namespace AST { // instanciate global variables (private API) namespace AST_INTERNAL { - bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit; + bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit; bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; AstNode *current_ast, *current_ast_mod; std::map current_scope; @@ -267,10 +267,12 @@ void AstNode::dumpAst(FILE *f, std::string indent) const std::string type_name = type2str(type); fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum); - if (id2ast) - fprintf(f, " [%p -> %p]", this, id2ast); - else - fprintf(f, " [%p]", this); + if (!flag_no_dump_ptr) { + if (id2ast) + fprintf(f, " [%p -> %p]", this, id2ast); + else + fprintf(f, " [%p]", this); + } if (!str.empty()) fprintf(f, " str='%s'", str.c_str()); @@ -1008,12 +1010,13 @@ static AstModule* process_module(AstNode *ast, bool defer) } // create AstModule instances for all modules in the AST tree and add them to 'design' -void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, +void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) { current_ast = ast; flag_dump_ast1 = dump_ast1; flag_dump_ast2 = dump_ast2; + flag_no_dump_ptr = no_dump_ptr; flag_dump_vlog = dump_vlog; flag_dump_rtlil = dump_rtlil; flag_nolatches = nolatches; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index d94199643..7e97bdb3b 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -274,7 +274,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library @@ -305,7 +305,7 @@ namespace AST namespace AST_INTERNAL { // internal state variables - extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit; + extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit; extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map current_scope; diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 911e36112..8dcc7c5aa 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -78,6 +78,9 @@ struct VerilogFrontend : public Frontend { log(" -dump_ast2\n"); log(" dump abstract syntax tree (after simplification)\n"); log("\n"); + log(" -no_dump_ptr\n"); + log(" do not include hex memory addresses in dump (easier to diff dumps)\n"); + log("\n"); log(" -dump_vlog\n"); log(" dump ast as Verilog code (after simplification)\n"); log("\n"); @@ -184,6 +187,7 @@ struct VerilogFrontend : public Frontend { { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; + bool flag_no_dump_ptr = false; bool flag_dump_vlog = false; bool flag_dump_rtlil = false; bool flag_nolatches = false; @@ -241,6 +245,10 @@ struct VerilogFrontend : public Frontend { flag_dump_ast2 = true; continue; } + if (arg == "-no_dump_ptr") { + flag_no_dump_ptr = true; + continue; + } if (arg == "-dump_vlog") { flag_dump_vlog = true; continue; @@ -381,7 +389,7 @@ struct VerilogFrontend : public Frontend { if (flag_nodpi) error_on_dpi_function(current_ast); - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; From 93d19dc2fb35335607e67cab8ecf5ebe28268a1f Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 23 Aug 2018 14:35:11 -0700 Subject: [PATCH 172/184] Add support for module instances. Don't pad logical operands to one bit. Use operand width and signedness in $reduce_bool. Shift amounts are unsigned and shouldn't be padded. Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0). --- backends/firrtl/firrtl.cc | 139 +++++++++++++++++++++++++++++++++----- 1 file changed, 122 insertions(+), 17 deletions(-) diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 4f56f498c..14fae1a83 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -28,10 +28,32 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +bool defparam, noattr; pool used_names; dict namecache; int autoid_counter; +typedef unsigned FDirection; +static const FDirection NODIRECTION = 0x0; +static const FDirection IN = 0x1; +static const FDirection OUT = 0x2; +static const FDirection INOUT = 0x3; + +// Get a port direction with respect to a specific module. +FDirection getPortFDirection(IdString id, Module *module) +{ + Wire *wire = module->wires_.at(id); + FDirection direction = NODIRECTION; + if (wire && wire->port_id) + { + if (wire->port_input) + direction |= IN; + if (wire->port_output) + direction |= OUT; + } + return direction; +} + string next_id() { string new_id; @@ -77,6 +99,8 @@ struct FirrtlWorker dict> reverse_wire_map; string unconn_id; + RTLIL::Design *design; + std::string indent; void register_reverse_wire_map(string id, SigSpec sig) { @@ -84,11 +108,11 @@ struct FirrtlWorker reverse_wire_map[sig[i]] = make_pair(id, i); } - FirrtlWorker(Module *module, std::ostream &f) : module(module), f(f) + FirrtlWorker(Module *module, std::ostream &f, RTLIL::Design *theDesign) : module(module), f(f), design(theDesign), indent(" ") { } - string make_expr(SigSpec sig) + string make_expr(const SigSpec &sig) { string expr; @@ -135,6 +159,74 @@ struct FirrtlWorker return expr; } + std::string fid(RTLIL::IdString internal_id) + { + const char *str = internal_id.c_str(); + return *str == '\\' ? str + 1 : str; + } + + + std::string cellname(RTLIL::Cell *cell) + { + return fid(cell->name).c_str(); + } + + void process_instance(RTLIL::Cell *cell, vector &wire_exprs) + { + // TODO: Deal with cell attributes + if (!noattr && !cell->attributes.empty()) { + + } + std::string cell_type = fid(cell->type); + + // TODO: Deal with cell parameters + if (!defparam && cell->parameters.size() > 0) { + + } + + std::string cell_name = cellname(cell); + std::string cell_name_comment; + if (cell_name != fid(cell->name)) + cell_name_comment = " /* " + fid(cell->name) + " */ "; + else + cell_name_comment = ""; + // Find the module corresponding to this instance. + auto instModule = design->module(cell->type); + wire_exprs.push_back(stringf("%s" "inst %s%s of %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), cell_type.c_str())); + + for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) { + if (it->second.size() > 0) { + const SigSpec &secondSig = it->second; + const std::string firstName = cell_name + "." + make_id(it->first); + const std::string secondName = make_expr(secondSig); + // Find the direction for this port. + FDirection dir = getPortFDirection(it->first, instModule); + std::string source, sink; + switch (dir) { + case INOUT: + log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", log_id(cell_type), log_signal(it->second)); + case OUT: + source = firstName; + sink = secondName; + break; + case NODIRECTION: + log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", log_id(cell_type), log_signal(it->second)); + /* FALL_THROUGH */ + case IN: + source = secondName; + sink = firstName; + break; + default: + log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", log_id(cell_type), log_signal(it->second), dir); + break; + } + wire_exprs.push_back(stringf("\n%s%s <= %s", indent.c_str(), sink.c_str(), source.c_str())); + } + } + wire_exprs.push_back(stringf("\n")); + + } + void run() { f << stringf(" module %s:\n", make_id(module->name)); @@ -142,21 +234,28 @@ struct FirrtlWorker for (auto wire : module->wires()) { + const auto wireName = make_id(wire->name); if (wire->port_id) { if (wire->port_input && wire->port_output) log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire)); port_decls.push_back(stringf(" %s %s: UInt<%d>\n", wire->port_input ? "input" : "output", - make_id(wire->name), wire->width)); + wireName, wire->width)); } else { - wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", make_id(wire->name), wire->width)); + wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", wireName, wire->width)); } } for (auto cell : module->cells()) { + // Is this cell is a module instance? + if (cell->type[0] != '$') + { + process_instance(cell, wire_exprs); + continue; + } if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor")) { string y_id = make_id(cell->name); @@ -169,7 +268,10 @@ struct FirrtlWorker a_expr = "asSInt(" + a_expr + ")"; } - a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width); + // Don't use the results of logical operations (a single bit) to control padding + if (!(cell->type.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width == 1) ) { + a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width); + } string primop; bool always_uint = false; @@ -187,9 +289,12 @@ struct FirrtlWorker a_expr = stringf("xorr(%s)", a_expr.c_str()); } if (cell->type == "$reduce_bool") { - primop = "neq"; - a_expr = stringf("%s, UInt(0)", a_expr.c_str()); - } + primop = "neq"; + // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand. + bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool(); + int a_width = cell->parameters.at("\\A_WIDTH").as_int(); + a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width); + } string expr = stringf("%s(%s)", primop.c_str(), a_expr.c_str()); @@ -215,16 +320,16 @@ struct FirrtlWorker if (cell->parameters.at("\\A_SIGNED").as_bool()) { a_expr = "asSInt(" + a_expr + ")"; } - if (cell->parameters.at("\\A_SIGNED").as_bool() & (cell->type != "$shr")) { - b_expr = "asSInt(" + b_expr + ")"; + // Shift amount is always unsigned, and needn't be padded to result width. + if (!cell->type.in("$shr", "$sshr", "$shl", "$sshl")) { + if (cell->parameters.at("\\B_SIGNED").as_bool()) { + b_expr = "asSInt(" + b_expr + ")"; + } + b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width); } a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width); - if ((cell->type != "$shl") && (cell->type != "$sshl")) { - b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width); - } - if (cell->parameters.at("\\A_SIGNED").as_bool() & (cell->type == "$shr")) { a_expr = "asUInt(" + a_expr + ")"; } @@ -494,14 +599,14 @@ struct FirrtlWorker if (is_valid) { if (make_unconn_id) { wire_decls.push_back(stringf(" wire %s: UInt<1>\n", unconn_id.c_str())); - cell_exprs.push_back(stringf(" %s is invalid\n", unconn_id.c_str())); + wire_decls.push_back(stringf(" %s is invalid\n", unconn_id.c_str())); } wire_exprs.push_back(stringf(" %s <= %s\n", make_id(wire->name), expr.c_str())); } else { if (make_unconn_id) { unconn_id.clear(); } - wire_exprs.push_back(stringf(" %s is invalid\n", make_id(wire->name))); + wire_decls.push_back(stringf(" %s is invalid\n", make_id(wire->name))); } } @@ -570,7 +675,7 @@ struct FirrtlBackend : public Backend { for (auto module : design->modules()) { - FirrtlWorker worker(module, *f); + FirrtlWorker worker(module, *f, design); worker.run(); } From 306a010e199d9318472c9c08eb16117bd83c7257 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 25 Aug 2018 16:20:44 +0200 Subject: [PATCH 173/184] static link flag on main executable --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c1e5c789d..18bf303b1 100644 --- a/Makefile +++ b/Makefile @@ -158,7 +158,7 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H" else ifeq ($(CONFIG),gcc-static) LD = $(CXX) -LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s +LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static LDLIBS := $(filter-out -lrt,$(LDLIBS)) CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) CXXFLAGS += -std=c++11 -Os From 9e845bd25460d7b8287cf3ea5147040689940f49 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 27 Aug 2018 13:27:05 +0200 Subject: [PATCH 174/184] Add ENABLE_GCOV build option Signed-off-by: Clifford Wolf --- Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Makefile b/Makefile index 18bf303b1..7eb3971f7 100644 --- a/Makefile +++ b/Makefile @@ -19,6 +19,7 @@ ENABLE_LIBYOSYS := 0 ENABLE_PROTOBUF := 0 # other configuration flags +ENABLE_GCOV := 0 ENABLE_GPROF := 0 ENABLE_DEBUG := 0 ENABLE_NDEBUG := 0 @@ -312,6 +313,11 @@ endif endif endif +ifeq ($(ENABLE_GCOV),1) +CXXFLAGS += --coverage +LDFLAGS += --coverage +endif + ifeq ($(ENABLE_GPROF),1) CXXFLAGS += -pg LDFLAGS += -pg @@ -709,6 +715,11 @@ config-msys2: clean config-msys2-64: clean echo 'CONFIG := msys2-64' > Makefile.conf +config-gcov: clean + echo 'CONFIG := gcc' > Makefile.conf + echo 'ENABLE_GCOV := 1' >> Makefile.conf + echo 'ENABLE_DEBUG := 1' >> Makefile.conf + config-gprof: clean echo 'CONFIG := gcc' > Makefile.conf echo 'ENABLE_GPROF := 1' >> Makefile.conf From ddc1761f1a443ea9560c67cfc126160ba7254a39 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 27 Aug 2018 14:22:21 +0200 Subject: [PATCH 175/184] Add "make coverage" Signed-off-by: Clifford Wolf --- .gitignore | 4 ++++ Makefile | 8 +++++++- frontends/ilang/.gitignore | 2 +- frontends/ilang/Makefile.inc | 7 +++---- frontends/ilang/ilang_lexer.l | 2 +- frontends/verilog/.gitignore | 2 +- frontends/verilog/Makefile.inc | 7 +++---- frontends/verilog/verilog_lexer.l | 2 +- 8 files changed, 21 insertions(+), 13 deletions(-) diff --git a/.gitignore b/.gitignore index cd624f233..4fce690ec 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,8 @@ *.d .*.swp *.gch +*.gcda +*.gcno /.cproject /.project /.settings @@ -10,6 +12,8 @@ /qtcreator.config /qtcreator.creator /qtcreator.creator.user +/coverage.info +/coverage_html /Makefile.conf /abc /viz.js diff --git a/Makefile b/Makefile index 7eb3971f7..39a361a5f 100644 --- a/Makefile +++ b/Makefile @@ -650,6 +650,12 @@ clean-abc: mrproper: clean git clean -xdf +coverage: + ./yosys -qp 'help; help -all' + rm -rf coverage.info coverage_html + lcov --capture -d . --no-external -o coverage.info + genhtml coverage.info --output-directory coverage_html + qtcreator: { for file in $(basename $(OBJS)); do \ for prefix in cc y l; do if [ -f $${file}.$${prefix} ]; then echo $$file.$${prefix}; fi; done \ @@ -740,6 +746,6 @@ echo-git-rev: -include kernel/*.d -include techlibs/*/*.d -.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator +.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator coverage vcxsrc mxebin .PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo diff --git a/frontends/ilang/.gitignore b/frontends/ilang/.gitignore index 43106a814..f586b33c7 100644 --- a/frontends/ilang/.gitignore +++ b/frontends/ilang/.gitignore @@ -1,4 +1,4 @@ ilang_lexer.cc ilang_parser.output ilang_parser.tab.cc -ilang_parser.tab.h +ilang_parser.tab.hh diff --git a/frontends/ilang/Makefile.inc b/frontends/ilang/Makefile.inc index e2a476c93..6f1f0e8fc 100644 --- a/frontends/ilang/Makefile.inc +++ b/frontends/ilang/Makefile.inc @@ -1,15 +1,14 @@ GENFILES += frontends/ilang/ilang_parser.tab.cc -GENFILES += frontends/ilang/ilang_parser.tab.h +GENFILES += frontends/ilang/ilang_parser.tab.hh GENFILES += frontends/ilang/ilang_parser.output GENFILES += frontends/ilang/ilang_lexer.cc frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y $(Q) mkdir -p $(dir $@) - $(P) $(BISON) -d -r all -b frontends/ilang/ilang_parser $< - $(Q) mv frontends/ilang/ilang_parser.tab.c frontends/ilang/ilang_parser.tab.cc + $(P) $(BISON) -o $@ -d -r all -b frontends/ilang/ilang_parser $< -frontends/ilang/ilang_parser.tab.h: frontends/ilang/ilang_parser.tab.cc +frontends/ilang/ilang_parser.tab.hh: frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l $(Q) mkdir -p $(dir $@) diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l index 842388548..d8e01ae4d 100644 --- a/frontends/ilang/ilang_lexer.l +++ b/frontends/ilang/ilang_lexer.l @@ -30,7 +30,7 @@ #endif #include "frontends/ilang/ilang_frontend.h" -#include "ilang_parser.tab.h" +#include "ilang_parser.tab.hh" USING_YOSYS_NAMESPACE diff --git a/frontends/verilog/.gitignore b/frontends/verilog/.gitignore index 1d4ae9e5c..aadbcdcdd 100644 --- a/frontends/verilog/.gitignore +++ b/frontends/verilog/.gitignore @@ -1,4 +1,4 @@ verilog_lexer.cc verilog_parser.output verilog_parser.tab.cc -verilog_parser.tab.h +verilog_parser.tab.hh diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc index a06c1d5ab..dbaace585 100644 --- a/frontends/verilog/Makefile.inc +++ b/frontends/verilog/Makefile.inc @@ -1,15 +1,14 @@ GENFILES += frontends/verilog/verilog_parser.tab.cc -GENFILES += frontends/verilog/verilog_parser.tab.h +GENFILES += frontends/verilog/verilog_parser.tab.hh GENFILES += frontends/verilog/verilog_parser.output GENFILES += frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y $(Q) mkdir -p $(dir $@) - $(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser $< - $(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc + $(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $< -frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc +frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l $(Q) mkdir -p $(dir $@) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 0134416c1..83921bf0b 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -42,7 +42,7 @@ #include "kernel/log.h" #include "frontends/verilog/verilog_frontend.h" #include "frontends/ast/ast.h" -#include "verilog_parser.tab.h" +#include "verilog_parser.tab.hh" USING_YOSYS_NAMESPACE using namespace AST; From 380c6f0e978869099d5b2c5dd81d8065a1f5c3cc Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 27 Aug 2018 10:18:33 -0700 Subject: [PATCH 176/184] Remove unused functions. --- backends/firrtl/firrtl.cc | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 14fae1a83..94236d0b1 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -28,7 +28,6 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -bool defparam, noattr; pool used_names; dict namecache; int autoid_counter; @@ -173,17 +172,8 @@ struct FirrtlWorker void process_instance(RTLIL::Cell *cell, vector &wire_exprs) { - // TODO: Deal with cell attributes - if (!noattr && !cell->attributes.empty()) { - - } std::string cell_type = fid(cell->type); - // TODO: Deal with cell parameters - if (!defparam && cell->parameters.size() > 0) { - - } - std::string cell_name = cellname(cell); std::string cell_name_comment; if (cell_name != fid(cell->name)) From 92896a58beb66d633f787c30ec291f6be8d9e0e0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 28 Aug 2018 13:11:41 +0200 Subject: [PATCH 177/184] Remove mercurial, since it is not needed anymore --- .travis.yml | 5 ----- Brewfile | 1 - 2 files changed, 6 deletions(-) diff --git a/.travis.yml b/.travis.yml index fbb4018af..321c3325f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -28,7 +28,6 @@ matrix: - tcl-dev - libffi-dev - git - - mercurial - graphviz - xdot - pkg-config @@ -53,7 +52,6 @@ matrix: - tcl-dev - libffi-dev - git - - mercurial - graphviz - xdot - pkg-config @@ -78,7 +76,6 @@ matrix: - tcl-dev - libffi-dev - git - - mercurial - graphviz - xdot - pkg-config @@ -104,7 +101,6 @@ matrix: - tcl-dev - libffi-dev - git - - mercurial - graphviz - xdot - pkg-config @@ -129,7 +125,6 @@ matrix: - tcl-dev - libffi-dev - git - - mercurial - graphviz - xdot - pkg-config diff --git a/Brewfile b/Brewfile index d7cd05bf1..0c58ce161 100644 --- a/Brewfile +++ b/Brewfile @@ -3,7 +3,6 @@ brew "flex" brew "gawk" brew "libffi" brew "git" -brew "mercurial" brew "graphviz" brew "pkg-config" brew "python3" From d36d11936f6725b9fc0702e9406bc55533d8e273 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= Date: Tue, 28 Aug 2018 08:17:33 -0700 Subject: [PATCH 178/184] Add GCC to osx deps (#620) * Add GCC to osx deps * Force gcc-7 install --- .travis/setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis/setup.sh b/.travis/setup.sh index 81ff37742..068515786 100755 --- a/.travis/setup.sh +++ b/.travis/setup.sh @@ -64,7 +64,7 @@ if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then brew tap Homebrew/bundle brew bundle brew install ccache - brew install gcc + brew install gcc@7 echo echo -en 'travis_fold:end:before_install.brew\\r' echo From 0b7a18470bbd35214fdeff204f9c20964e69b5c5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 30 Aug 2018 12:26:26 +0200 Subject: [PATCH 179/184] Add "make ystests" Signed-off-by: Clifford Wolf --- .gitignore | 1 + CodingReadme | 1 + Makefile | 8 ++++++++ 3 files changed, 10 insertions(+) diff --git a/.gitignore b/.gitignore index 4fce690ec..48ce458c7 100644 --- a/.gitignore +++ b/.gitignore @@ -34,3 +34,4 @@ /libyosys.so /tests/unit/bintest/ /tests/unit/objtest/ +/tests/ystests diff --git a/CodingReadme b/CodingReadme index 4ab132a63..b64e79178 100644 --- a/CodingReadme +++ b/CodingReadme @@ -373,6 +373,7 @@ Finally run all tests with "make config-{clang,gcc,gcc-4.8}": cd ~yosys make clean make test + make ystests make vloghtb make install diff --git a/Makefile b/Makefile index 39a361a5f..7698047ec 100644 --- a/Makefile +++ b/Makefile @@ -585,6 +585,14 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS) @echo " Passed \"make vloghtb\"." @echo "" +ystests: $(TARGETS) $(EXTRA_TARGETS) + rm -rf tests/ystests + git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests + +PATH="$$PWD:$$PATH" cd tests/ystests && $(MAKE) + @echo "" + @echo " Finished \"make ystests\"." + @echo "" + # Unit test unit-test: libyosys.so @$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \ From 5d9d22f66d512d33b2c1a13c4f1a20f944e6acc3 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 4 Sep 2018 20:06:10 +0200 Subject: [PATCH 180/184] Add "verific -L " option Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 11 +++++++++++ frontends/verific/verific.h | 2 ++ frontends/verific/verificsva.cc | 5 +++-- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 1dd6d7e24..c5fa58313 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -64,6 +64,7 @@ YOSYS_NAMESPACE_BEGIN int verific_verbose; bool verific_import_pending; string verific_error_msg; +int verific_sva_fsm_limit; vector verific_incdirs, verific_libdirs; @@ -1618,6 +1619,8 @@ struct VerificExtNets void verific_import(Design *design, std::string top) { + verific_sva_fsm_limit = 16; + std::set nl_todo, nl_done; { @@ -1789,6 +1792,9 @@ struct VerificPass : public Pass { log(" -nosva\n"); log(" Ignore SVA properties, do not infer checker logic.\n"); log("\n"); + log(" -L \n"); + log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n"); + log("\n"); log(" -n\n"); log(" Keep all Verific names on instances and nets. By default only\n"); log(" user-declared names are preserved.\n"); @@ -1830,6 +1836,7 @@ struct VerificPass : public Pass { } verific_verbose = 0; + verific_sva_fsm_limit = 16; const char *release_str = Message::ReleaseString(); time_t release_time = Message::ReleaseDate(); @@ -2036,6 +2043,10 @@ struct VerificPass : public Pass { mode_nosva = true; continue; } + if (args[argidx] == "-L" && argidx+1 < GetSize(args)) { + verific_sva_fsm_limit = atoi(args[++argidx].c_str()); + continue; + } if (args[argidx] == "-n") { mode_names = true; continue; diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index cbd9314db..334a436af 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -101,6 +101,8 @@ void verific_import_sva_cover(VerificImporter *importer, Verific::Instance *inst void verific_import_sva_trigger(VerificImporter *importer, Verific::Instance *inst); bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net); +extern int verific_sva_fsm_limit; + YOSYS_NAMESPACE_END #endif diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 85b842186..cdc9ece8c 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -466,13 +466,14 @@ struct SvaFsm dnode.ctrl.sort_and_unify(); - if (GetSize(dnode.ctrl) > 16) { + if (GetSize(dnode.ctrl) > verific_sva_fsm_limit) { if (verific_verbose >= 2) { log(" detected state explosion in DFSM generation:\n"); dump(); log(" ctrl signal: %s\n", log_signal(dnode.ctrl)); } - log_error("SVA DFSM state ctrl signal has %d (>16) bits. Stopping to prevent exponential design size explosion.\n", GetSize(dnode.ctrl)); + log_error("SVA DFSM state ctrl signal has %d (>%d) bits. Stopping to prevent exponential design size explosion.\n", + GetSize(dnode.ctrl), verific_sva_fsm_limit); } for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++) From 12440fcc8f705c117b5f91fae24b7e5c4fbf8560 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 6 Sep 2018 00:18:01 +0200 Subject: [PATCH 181/184] Add $lut support to Verilog back-end Signed-off-by: Clifford Wolf --- backends/verilog/verilog_backend.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 44e4e5f97..d3262ec47 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -779,6 +779,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$lut") + { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Y")); + f << stringf(" = "); + dump_const(f, cell->parameters.at("\\LUT")); + f << stringf(" >> "); + dump_attributes(f, "", cell->attributes, ' '); + dump_sigspec(f, cell->getPort("\\A")); + f << stringf(";\n"); + return true; + } + if (cell->type == "$dffsr") { SigSpec sig_clk = cell->getPort("\\CLK"); From 51f1bbeeb08020a9b739d2bd0cf4d79ca6e62015 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 10 Sep 2018 11:57:24 +0200 Subject: [PATCH 182/184] Add iCE40 SB_SPRAM256KA simulation model Signed-off-by: Clifford Wolf --- techlibs/ice40/cells_sim.v | 39 +++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 9f73aeb07..e0a07af32 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -920,19 +920,40 @@ parameter A_SIGNED = 1'b0; parameter B_SIGNED = 1'b0; endmodule -(* blackbox *) -module SB_SPRAM256KA( +module SB_SPRAM256KA ( input [13:0] ADDRESS, input [15:0] DATAIN, input [3:0] MASKWREN, - input WREN, - input CHIPSELECT, - input CLOCK, - input STANDBY, - input SLEEP, - input POWEROFF, - output [15:0] DATAOUT + input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF, + output reg [15:0] DATAOUT ); +`ifndef BLACKBOX + reg [15:0] mem [0:16383]; + wire off = SLEEP || !POWEROFF; + integer i; + + always @(negedge POWEROFF) begin + for (i = 0; i <= 16383; i = i+1) + mem[i] = 'bx; + end + + always @(posedge CLOCK, posedge off) begin + if (off) begin + DATAOUT <= 0; + end else + if (CHIPSELECT && !STANDBY && !WREN) begin + DATAOUT <= mem[ADDRESS]; + end else begin + if (CHIPSELECT && !STANDBY && WREN) begin + if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0]; + if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4]; + if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8]; + if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12]; + end + DATAOUT <= 'bx; + end + end +`endif endmodule (* blackbox *) From 75c1f8d241d67ebb6db56516b4f9fdb0a312aa0b Mon Sep 17 00:00:00 2001 From: Aman Goel Date: Mon, 10 Sep 2018 21:44:36 -0400 Subject: [PATCH 183/184] Minor revision to -expose in setundef pass Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort. --- passes/cmds/setundef.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 62d940ce6..a1dfa9b5c 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -162,7 +162,6 @@ struct SetundefPass : public Pass { continue; } if (args[argidx] == "-expose") { - got_value = true; expose_mode = true; continue; } @@ -212,6 +211,13 @@ struct SetundefPass : public Pass { } extra_args(args, argidx, design); + if (!got_value && expose_mode) { + log("Using default as -undef with -expose.\n"); + got_value = true; + worker.next_bit_mode = MODE_UNDEF; + worker.next_bit_state = 0; + } + if (expose_mode && !undriven_mode) log_cmd_error("Option -expose must be used with option -undriven.\n"); if (!got_value) From 5fe16c25b81d507fa41381eca70c5aada59db25f Mon Sep 17 00:00:00 2001 From: acw1251 Date: Wed, 12 Sep 2018 18:33:27 -0400 Subject: [PATCH 184/184] Fixed minor typo in "sim" help message --- passes/sat/sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index fadffcdbc..53e248adf 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -778,7 +778,7 @@ struct SimPass : public Pass { log(" number of cycles to simulate (default: 20)\n"); log("\n"); log(" -a\n"); - log(" include all nets in VCD output, nut just those with public names\n"); + log(" include all nets in VCD output, not just those with public names\n"); log("\n"); log(" -w\n"); log(" writeback mode: use final simulation state as new init state\n");