mirror of https://github.com/YosysHQ/yosys.git
chformal: Add -coverprecond option
This inserts $cover cells to cover the enable signal (precondition) for the selected formal cells.
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@ -55,6 +55,9 @@ struct ChformalPass : public Pass {
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log(" -skip <N>\n");
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log(" -skip <N>\n");
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log(" ignore activation of the constraint in the first <N> clock cycles\n");
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log(" ignore activation of the constraint in the first <N> clock cycles\n");
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log("\n");
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log("\n");
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log(" -coverprecond\n");
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log(" add a cover statement for the precondition (enable signal) of the cells\n");
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log("\n");
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log(" -assert2assume\n");
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log(" -assert2assume\n");
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log(" -assume2assert\n");
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log(" -assume2assert\n");
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log(" -live2fair\n");
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log(" -live2fair\n");
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@ -114,6 +117,10 @@ struct ChformalPass : public Pass {
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mode_arg = atoi(args[++argidx].c_str());
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mode_arg = atoi(args[++argidx].c_str());
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continue;
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continue;
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}
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}
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if (mode == 0 && args[argidx] == "-coverprecond") {
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mode = 'p';
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2assume") {
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if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2assume") {
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assert2assume = true;
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assert2assume = true;
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mode = 'c';
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mode = 'c';
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@ -263,6 +270,13 @@ struct ChformalPass : public Pass {
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cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
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cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
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}
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}
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else
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else
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if (mode =='p')
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{
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for (auto cell : constr_cells)
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module->addCover(NEW_ID, cell->getPort(ID::EN), State::S1,
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"$auto$coverprecond$" + cell->get_src_attribute());
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}
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else
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if (mode == 'c')
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if (mode == 'c')
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{
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{
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for (auto cell : constr_cells)
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for (auto cell : constr_cells)
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