mirror of https://github.com/YosysHQ/yosys.git
Fixed a bug in opt_const when optimizing 1-bit compares with constants
This commit is contained in:
parent
db10275251
commit
c6198ea5a8
|
@ -181,8 +181,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
|
||||||
RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
|
RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
|
||||||
|
|
||||||
if (a.is_fully_const()) {
|
if (a.is_fully_const()) {
|
||||||
RTLIL::SigSpec tmp = a;
|
RTLIL::SigSpec tmp;
|
||||||
a = b, b = tmp;
|
tmp = a, a = b, b = tmp;
|
||||||
|
cell->connections["\\A"] = a;
|
||||||
|
cell->connections["\\B"] = b;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (b.is_fully_const()) {
|
if (b.is_fully_const()) {
|
||||||
|
|
Loading…
Reference in New Issue