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Always use BLIF as ABC output format

This commit is contained in:
Clifford Wolf 2013-12-31 13:41:16 +01:00
parent 364f277afb
commit c616802ac7
5 changed files with 31 additions and 268 deletions
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1
passes/abc/Makefile.inc
View File

@ -1,7 +1,6 @@
ifeq ($(ENABLE_ABC),1) ifeq ($(ENABLE_ABC),1)
OBJS += passes/abc/abc.o OBJS += passes/abc/abc.o
OBJS += passes/abc/vlparse.o
OBJS += passes/abc/blifparse.o OBJS += passes/abc/blifparse.o
endif endif

17
passes/abc/abc.cc
View File

@ -36,7 +36,6 @@
#include <dirent.h> #include <dirent.h>
#include <sstream> #include <sstream>
#include "vlparse.h"
#include "blifparse.h" #include "blifparse.h"
struct gate_t struct gate_t
@ -481,10 +480,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
"%s -s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; strash; balance; dch; map; ", "%s -s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; strash; balance; dch; map; ",
exe_file.c_str(), tempdir_name, tempdir_name); exe_file.c_str(), tempdir_name, tempdir_name);
if (lut_mode) buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_blif %s/output.blif' 2>&1", tempdir_name);
buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_blif %s/output.blif' 2>&1", tempdir_name);
else
buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_verilog %s/output.v' 2>&1", tempdir_name);
errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand
f = popen(buffer, "r"); f = popen(buffer, "r");
@ -504,16 +500,13 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
} }
} }
if (asprintf(&p, "%s/%s", tempdir_name, lut_mode ? "output.blif" : "output.v") < 0) abort(); if (asprintf(&p, "%s/%s", tempdir_name, "output.blif") < 0) log_abort();
f = fopen(p, "rt"); f = fopen(p, "rt");
if (f == NULL) if (f == NULL)
log_error("Can't open ABC output file `%s'.\n", p); log_error("Can't open ABC output file `%s'.\n", p);
#if 0
RTLIL::Design *mapped_design = new RTLIL::Design; RTLIL::Design *mapped_design = abc_parse_blif(f);
frontend_register["verilog"]->execute(f, p, std::vector<std::string>(), mapped_design);
#else
RTLIL::Design *mapped_design = lut_mode ? abc_parse_blif(f) : abc_parse_verilog(f);
#endif
fclose(f); fclose(f);
free(p); free(p);

26
passes/abc/blifparse.cc
View File

@ -101,6 +101,32 @@ RTLIL::Design *abc_parse_blif(FILE *f)
continue; continue;
} }
if (!strcmp(cmd, ".gate"))
{
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
module->add(cell);
char *p = strtok(NULL, " \t\r\n");
if (p == NULL)
goto error;
cell->type = RTLIL::escape_id(p);
while ((p = strtok(NULL, " \t\r\n")) != NULL) {
char *q = strchr(p, '=');
if (q == NULL || !q[0] || !q[1])
goto error;
*(q++) = 0;
if (module->wires.count(RTLIL::escape_id(q)) == 0) {
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = RTLIL::escape_id(q);
module->add(wire);
}
cell->connections[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q));
}
continue;
}
if (!strcmp(cmd, ".names")) if (!strcmp(cmd, ".names"))
{ {
char *p; char *p;

227
passes/abc/vlparse.cc
View File

@ -1,227 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "vlparse.h"
#include "kernel/log.h"
#include <stdio.h>
#include <string>
static int lex_line, lex_tok;
static std::string lex_str;
static int token(int tok)
{
lex_tok = tok;
#if 0
if (lex_tok == 256)
fprintf(stderr, "STR in line %d: >>%s<<\n", lex_line, lex_str.c_str());
else if (tok >= 32 && tok < 255)
fprintf(stderr, "CHAR in line %d: >>%c<<\n", lex_line, lex_tok);
else
fprintf(stderr, "CHAR in line %d: %d\n", lex_line, lex_tok);
#endif
return tok;
}
static int lex(FILE *f)
{
int ch = getc(f);
while (ch == ' ' || ch == '\t' || ch == '\n') {
if (ch == '\n')
lex_line++;
ch = getc(f);
}
if (ch <= 0 || 255 < ch)
return token(lex_tok);
if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') ||
('0' <= ch && ch <= '9') || ch == '_' || ch == '\'') {
lex_str = char(ch);
while (1) {
ch = getc(f);
if (('a' <= ch && ch <= 'z') || ('A' <= ch && ch <= 'Z') ||
('0' <= ch && ch <= '9') || ch == '_' || ch == '\'') {
lex_str += char(ch);
continue;
}
break;
}
ungetc(ch, f);
return token(256);
}
if (ch == '/') {
ch = getc(f);
if (ch == '/') {
while (ch != '\n')
ch = getc(f);
ungetc(ch, f);
return lex(f);
}
ungetc(ch, f);
return token('/');
}
return token(ch);
}
RTLIL::Design *abc_parse_verilog(FILE *f)
{
RTLIL::Design *design = new RTLIL::Design;
RTLIL::Module *module;
RTLIL::Wire *wire;
RTLIL::Cell *cell;
int port_count = 1;
lex_line = 1;
// parse module header
if (lex(f) != 256 || lex_str != "module")
goto error;
if (lex(f) != 256)
goto error;
module = new RTLIL::Module;
module->name = "\\" + lex_str;
design->modules[module->name] = module;
if (lex(f) != '(')
goto error;
while (lex(f) != ')') {
if (lex_tok != 256 && lex_tok != ',')
goto error;
}
if (lex(f) != ';')
goto error;
// parse module body
while (1)
{
if (lex(f) != 256)
goto error;
if (lex_str == "endmodule")
return design;
if (lex_str == "input" || lex_str == "output" || lex_str == "wire")
{
std::string mode = lex_str;
while (lex(f) != ';') {
if (lex_tok != 256 && lex_tok != ',')
goto error;
if (lex_tok == 256) {
// printf("%s [%s]\n", mode.c_str(), lex_str.c_str());
wire = new RTLIL::Wire;
wire->name = "\\" + lex_str;
if (mode == "input") {
wire->port_id = port_count++;
wire->port_input = true;
}
if (mode == "output") {
wire->port_id = port_count++;
wire->port_output = true;
}
module->wires[wire->name] = wire;
}
}
}
else if (lex_str == "assign")
{
std::string lhs, rhs;
if (lex(f) != 256)
goto error;
lhs = lex_str;
if (lex(f) != '=')
goto error;
if (lex(f) != 256)
goto error;
rhs = lex_str;
if (lex(f) != ';')
goto error;
if (module->wires.count(RTLIL::escape_id(lhs)) == 0)
goto error;
if (rhs == "1'b0")
module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), RTLIL::SigSpec(0, 1)));
else if (rhs == "1'b1")
module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), RTLIL::SigSpec(1, 1)));
else if (module->wires.count(RTLIL::escape_id(rhs)) > 0)
module->connections.push_back(RTLIL::SigSig(module->wires.at(RTLIL::escape_id(lhs)), module->wires.at(RTLIL::escape_id(rhs))));
else
goto error;
}
else
{
std::string cell_type = lex_str;
if (lex(f) != 256)
goto error;
std::string cell_name = lex_str;
if (lex(f) != '(')
goto error;
// printf("cell [%s] [%s]\n", cell_type.c_str(), cell_name.c_str());
cell = new RTLIL::Cell;
cell->type = "\\" + cell_type;
cell->name = "\\" + cell_name;
module->cells[cell->name] = cell;
lex(f);
while (lex_tok != ')')
{
if (lex_tok != '.' || lex(f) != 256)
goto error;
std::string cell_port = lex_str;
if (lex(f) != '(' || lex(f) != 256)
goto error;
std::string wire_name = lex_str;
// printf(" [%s] <- [%s]\n", cell_port.c_str(), wire_name.c_str());
if (module->wires.count("\\" + wire_name) == 0)
goto error;
cell->connections["\\" + cell_port] = RTLIL::SigSpec(module->wires["\\" + wire_name]);
if (lex(f) != ')' || (lex(f) != ',' && lex_tok != ')'))
goto error;
while (lex_tok == ',')
lex(f);
}
if (lex(f) != ';')
goto error;
}
}
error:
log_error("Syntax error in line %d!\n", lex_line);
// delete design;
// return NULL;
}

28
passes/abc/vlparse.h
View File

@ -1,28 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef ABC_VLPARSE
#define ABC_VLPARSE
#include "kernel/rtlil.h"
extern RTLIL::Design *abc_parse_verilog(FILE *f);
#endif