mirror of https://github.com/YosysHQ/yosys.git
Added pattern support to "ls" command
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@ -1004,59 +1004,64 @@ struct CdPass : public Pass {
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}
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}
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} CdPass;
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} CdPass;
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template<typename T>
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static int log_matches(const char *title, std::string pattern, T list)
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{
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std::vector<std::string> matches;
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for (auto &it : list)
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if (pattern.empty() || match_ids(it.first, pattern))
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matches.push_back(it.first);
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if (matches.empty())
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return 0;
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log("\n%d %s:\n", int(matches.size()), title);
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for (auto &id : matches)
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log(" %s\n", RTLIL::id2cstr(id));
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return matches.size();
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}
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struct LsPass : public Pass {
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struct LsPass : public Pass {
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LsPass() : Pass("ls", "list modules or objects in modules") { }
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LsPass() : Pass("ls", "list modules or objects in modules") { }
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virtual void help()
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virtual void help()
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{
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log("\n");
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log(" ls\n");
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log(" ls [pattern]\n");
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log("\n");
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log("\n");
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log("When no active module is selected, this prints a list of all module.\n");
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log("When no active module is selected, this prints a list of all modules.\n");
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log("\n");
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log("\n");
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log("When an active module is selected, this prints a list of objects in the module.\n");
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log("When an active module is selected, this prints a list of objects in the module.\n");
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log("\n");
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log("\n");
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log("If a pattern is given, the objects matching the pattern are printed\n");
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log("\n");
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}
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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{
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if (args.size() != 1)
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std::string pattern;
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int counter = 0;
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if (args.size() != 1 && args.size() != 2)
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log_cmd_error("Invalid number of arguments.\n");
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log_cmd_error("Invalid number of arguments.\n");
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if (args.size() == 2)
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pattern = args.at(1);
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if (design->selected_active_module.empty())
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if (design->selected_active_module.empty())
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{
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{
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log("\n%d modules:\n", int(design->modules.size()));
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counter += log_matches("modules", pattern, design->modules);
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for (auto &it : design->modules)
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log(" %s\n", RTLIL::id2cstr(it.first));
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}
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}
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else
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else
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if (design->modules.count(design->selected_active_module) > 0)
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if (design->modules.count(design->selected_active_module) > 0)
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{
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{
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RTLIL::Module *module = design->modules.at(design->selected_active_module);
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RTLIL::Module *module = design->modules.at(design->selected_active_module);
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counter += log_matches("wires", pattern, module->wires);
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if (module->wires.size()) {
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counter += log_matches("memories", pattern, module->memories);
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log("\n%d wires:\n", int(module->wires.size()));
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counter += log_matches("cells", pattern, module->cells);
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for (auto &it : module->wires)
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counter += log_matches("processes", pattern, module->processes);
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log(" %s\n", RTLIL::id2cstr(it.first));
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}
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}
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if (module->memories.size()) {
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// log("\nfound %d item%s.\n", counter, counter == 1 ? "" : "s");
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log("\n%d memories:\n", int(module->memories.size()));
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for (auto &it : module->memories)
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log(" %s\n", RTLIL::id2cstr(it.first));
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}
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if (module->cells.size()) {
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log("\n%d cells:\n", int(module->cells.size()));
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for (auto &it : module->cells)
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log(" %s\n", RTLIL::id2cstr(it.first));
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}
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if (module->processes.size()) {
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log("\n%d processes:\n", int(module->processes.size()));
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for (auto &it : module->processes)
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log(" %s\n", RTLIL::id2cstr(it.first));
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}
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}
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}
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}
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} LsPass;
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} LsPass;
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