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Make multiplier wider, do not do tech independent synth

This commit is contained in:
Eddie Hung 2019-08-22 12:17:25 -07:00
parent d945b8a357
commit c5754d9e8b
2 changed files with 6 additions and 8 deletions
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7
tests/ice40/mul.v
View File

@ -1,10 +1,9 @@
module top
(
input [3:0] x,
input [3:0] y,
input [5:0] x,
input [5:0] y,
output [3:0] A,
output [3:0] B
output [11:0] A,
);
assign A = x * y;

7
tests/ice40/mul.ys
View File

@ -1,9 +1,8 @@
read_verilog mul.v
hierarchy -top top
synth -flatten -run coarse # technology-independent coarse grained synthesis
#synth -flatten -run coarse # technology-independent coarse grained synthesis
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 15 t:SB_LUT4
select -assert-count 3 t:SB_CARRY
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
select -assert-count 1 t:SB_MAC16
select -assert-none t:SB_MAC16 %% t:* %D