mirror of https://github.com/YosysHQ/yosys.git
Bugfix in satgen for cells with wider in- than outputs.
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@ -166,7 +166,15 @@ struct SatGen
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void undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)
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void undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)
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{
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{
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assert(model_undef);
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assert(model_undef);
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ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));
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assert(vec_y.size() == vec_yy.size());
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if (vec_y.size() > vec_undef.size()) {
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std::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());
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std::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());
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ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));
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} else {
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assert(vec_y.size() == vec_undef.size());
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ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));
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}
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}
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}
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bool importCell(RTLIL::Cell *cell, int timestep = -1)
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bool importCell(RTLIL::Cell *cell, int timestep = -1)
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