mirror of https://github.com/YosysHQ/yosys.git
Documentation improvements etc.
- Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
This commit is contained in:
Ruben Undheim
parent
a36d1701dd
commit
c50afc4246
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@ -452,6 +452,9 @@ from SystemVerilog:
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into a design with ``read_verilog``, all its packages are available to
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SystemVerilog files being read into the same design afterwards.
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- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
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ports are inputs or outputs are supported.
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Building the documentation
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==========================
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@ -2,6 +2,7 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -1086,6 +1087,8 @@ AstModule::~AstModule()
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delete ast;
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}
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// When an interface instance is found in a module, the whole RTLIL for the module will be rederived again
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// from AST. The interface members are copied into the AST module with the prefix of the interface.
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void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces)
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{
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bool is_top = false;
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@ -1101,23 +1104,33 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
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new_ast->children.push_back(wire);
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}
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}
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// The old module will be deleted. Rename and mark for deletion:
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std::string original_name = this->name.str();
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std::string changed_name = original_name + "_before_replacing_local_interfaces";
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design->rename(this, changed_name);
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this->set_bool_attribute("\\to_delete");
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// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
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// new module.
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if (this->get_bool_attribute("\\initial_top")) {
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this->attributes.erase("\\initial_top");
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is_top = true;
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}
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// Generate RTLIL from AST for the new module and add to the design:
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AstModule *newmod = process_module(new_ast, false);
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design->add(newmod);
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RTLIL::Module* mod = design->module(original_name);
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if (is_top)
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mod->set_bool_attribute("\\top");
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// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
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mod->set_bool_attribute("\\interfaces_replaced_in_module");
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}
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// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
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// This method is used to explode the interface when the interface is a port of the module (not instantiated inside)
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail)
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{
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AstNode *new_ast = NULL;
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@ -1140,9 +1153,12 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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if (!design->has(modname)) {
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new_ast->str = modname;
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// Iterate over all interfaces which are ports in this module:
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for(auto &intf : interfaces) {
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RTLIL::Module * intfmodule = intf.second;
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std::string intfname = intf.first.str();
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// Check if a modport applies for the interface port:
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AstNode *modport = NULL;
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if (modports.count(intfname) > 0) {
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std::string interface_modport = modports.at(intfname).str();
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@ -1150,12 +1166,13 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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AstNode *ast_node_of_interface = ast_module_of_interface->ast;
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for (auto &ch : ast_node_of_interface->children) {
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if (ch->type == AST_MODPORT) {
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if (ch->str == interface_modport) {
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if (ch->str == interface_modport) { // Modport found
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modport = ch;
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}
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}
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}
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}
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// Iterate over all wires in the interface and add them to the module:
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for (auto &wire_it : intfmodule->wires_){
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AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
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std::string origname = log_id(wire_it.first);
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@ -1163,10 +1180,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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wire->str = newname;
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if (modport != NULL) {
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bool found_in_modport = false;
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// Search for the current wire in the wire list for the current modport
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for (auto &ch : modport->children) {
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if (ch->type == AST_MODPORTMEMBER) {
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std::string compare_name = "\\" + origname;
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if (ch->str == compare_name) {
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if (ch->str == compare_name) { // Found signal. The modport decides whether it is input or output
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found_in_modport = true;
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wire->is_input = ch->is_input;
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wire->is_output = ch->is_output;
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@ -1174,9 +1192,12 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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}
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}
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}
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if (found_in_modport) { // If not found in modport, do not create port
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if (found_in_modport) {
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new_ast->children.push_back(wire);
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}
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else { // If not found in modport, do not create port
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delete wire;
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}
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}
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else { // If no modport, set inout
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wire->is_input = true;
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@ -1191,10 +1212,13 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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RTLIL::Module* mod = design->module(modname);
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// Now that the interfaces have been exploded, we can delete the dummy port related to every interface.
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for(auto &intf : interfaces) {
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if(mod->wires_.count(intf.first)) {
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mod->wires_.erase(intf.first);
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mod->fixup_ports();
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// We copy the cell of the interface to the sub-module such that it can further be found if it is propagated
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// down to sub-sub-modules etc.
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RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name);
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new_subcell->set_bool_attribute("\\is_interface");
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}
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@ -1203,6 +1227,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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}
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}
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// If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module':
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if (interfaces.size() > 0) {
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mod->set_bool_attribute("\\interfaces_replaced_in_module");
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}
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@ -857,7 +857,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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case AST_MODPORTMEMBER:
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break;
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case AST_INTERFACEPORT: {
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// If a port in a module with unknown type is found, mark it as "is_interface=true"
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// If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
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// This is used by the hierarchy pass to know when it can replace interface connection with the individual
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// signals.
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RTLIL::Wire *wire = current_module->addWire(str, 1);
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@ -872,7 +872,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if(children[i]->type == AST_INTERFACEPORTTYPE) {
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std::string name_type = children[i]->str;
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size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
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if (ndots == 0) {
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// Separate the interface instance name from any modports:
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if (ndots == 0) { // Does not have modport
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wire->attributes["\\interface_type"] = name_type;
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}
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else {
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@ -882,11 +883,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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while(std::getline(name_type_stream, segment, '.')) {
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seglist.push_back(segment);
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}
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if (ndots == 1) {
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if (ndots == 1) { // Has modport
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wire->attributes["\\interface_type"] = seglist[0];
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wire->attributes["\\interface_modport"] = seglist[1];
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}
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else {
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else { // Erroneous port type
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log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
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}
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}
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@ -1034,7 +1035,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n",
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str.c_str());
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// If identifier is an interface, create a RTLIL::SigSpec object and set is_interface to true.
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// If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
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// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
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// with the individual signals:
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if (is_interface) {
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@ -1495,6 +1496,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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RTLIL::Cell *cell = current_module->addCell(str, "");
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cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
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// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
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cell->set_bool_attribute("\\module_not_derived");
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for (auto it = children.begin(); it != children.end(); it++) {
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@ -639,11 +639,9 @@ RTLIL::Module::~Module()
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delete it->second;
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}
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void RTLIL::Module::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces)
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void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
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{
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log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
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(void)local_interfaces; // To remove build warning
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(void)design; // To remove build warning
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}
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RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
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@ -2,6 +2,7 @@
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 Ruben Undheim <ruben.undheim@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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@ -145,6 +146,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
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std::string filename;
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// Always keep track of all derived interfaces available in the current module in 'interfaces_in_module':
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dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module;
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for (auto &cell_it : module->cells_)
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{
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@ -222,27 +224,29 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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RTLIL::Module *mod = design->module(cell->type);
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// Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to
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// some lists, so that they can be replaced further down:
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// some lists, so that the ports for sub-modules can be replaced further down:
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for (auto &conn : cell->connections()) {
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if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
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//const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type");
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//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module
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//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness)
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//}
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// Find if the sub-module has set a modport for the current interface connection:
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const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_modport");
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std::string interface_modport = "";
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for (auto &d : interface_modport_pool) {
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interface_modport = "\\" + d;
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}
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if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) {
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if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) { // Check if the connected wire is a potential interface in the parent module
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std::string interface_name_str = conn.second.bits()[0].wire->name.str();
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interface_name_str.replace(0,23,"");
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interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name
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interface_name_str = "\\" + interface_name_str;
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RTLIL::IdString interface_name = interface_name_str;
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bool will_do_step = false;
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if(module->get_bool_attribute("\\interfaces_replaced_in_module")) {
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bool not_found_interface = false;
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if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either
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if (interfaces_in_module.count(interface_name) > 0) { // Check if the interface instance is present in module
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RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name);
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for (auto &mod_wire : mod_replace_ports->wires_) {
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for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists.
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std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first);
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std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first);
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connections_to_add_name.push_back(RTLIL::IdString(signal_name1));
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@ -256,16 +260,18 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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}
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connections_to_remove.push_back(conn.first);
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interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name);
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// Add modports to a dict which will be passed to AstModule::derive
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if (interface_modport != "") {
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modports_used_in_submodule[conn.first] = interface_modport;
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}
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}
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else will_do_step = true;
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else not_found_interface = true;
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}
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else will_do_step = true;
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else not_found_interface = true;
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// If the interface instance has not already been derived in the module, we cannot complete at this stage. Set "has_interfaces_not_found"
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// which will delay the expansion of this cell:
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if (will_do_step) {
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if (not_found_interface) {
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// If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error:
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if(!(module->get_bool_attribute("\\cells_not_processed"))) {
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log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module));
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@ -348,13 +354,16 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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interfaces_in_module[cell->name] = derived_module;
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did_something = true;
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}
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// We unset 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell)
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// We clear 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell)
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cell->attributes.erase("\\module_not_derived");
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}
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// Setting a flag such that it can be known that we have been through all cells at least once, such that we can know whether to flag
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// an error because of interface instances not found:
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// Clear the attribute 'cells_not_processed' such that it can be known that we
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// have been through all cells at least once, and that we can know whether
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// to flag an error because of interface instances not found:
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module->attributes.erase("\\cells_not_processed");
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// If any interface instances were found in the module, we need to rederive it completely:
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if (interfaces_in_module.size() > 0 && !module->get_bool_attribute("\\interfaces_replaced_in_module")) {
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module->reprocess_module(design, interfaces_in_module);
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return did_something;
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@ -736,6 +745,7 @@ struct HierarchyPass : public Pass {
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}
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// The top module might have changed if interface instances have been detected in it:
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RTLIL::Module *tmp_top_mod = check_if_top_has_changed(design, top_mod);
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if (tmp_top_mod != NULL) {
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if (tmp_top_mod != top_mod){
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@ -744,6 +754,7 @@ struct HierarchyPass : public Pass {
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}
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}
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// Delete modules marked as 'to_delete':
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std::vector<RTLIL::Module *> modules_to_delete;
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for(auto &mod_it : design->modules_) {
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if (mod_it.second->get_bool_attribute("\\to_delete")) {
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