mirror of https://github.com/YosysHQ/yosys.git
Move only one consumer check outside of while loop
This commit is contained in:
parent
b7deaceadd
commit
c4e4902098
|
@ -189,16 +189,15 @@ struct MemoryDffWorker
|
|||
bool enable_invert = mux_cells_a.count(sig_data) != 0;
|
||||
Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
|
||||
check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
|
||||
|
||||
sig_data = sigmap(mux->getPort("\\Y"));
|
||||
for (auto bit : sig_data)
|
||||
if (sigbit_users_count[bit] > 1) {
|
||||
goto skip_ff_after_read_merging;
|
||||
}
|
||||
|
||||
en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
|
||||
} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
|
||||
|
||||
for (auto bit : sig_data)
|
||||
if (sigbit_users_count[bit] > 1) {
|
||||
goto skip_ff_after_read_merging;
|
||||
}
|
||||
|
||||
if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
|
||||
{
|
||||
disconnect_dff(sig_data);
|
||||
|
|
Loading…
Reference in New Issue