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Do not use default_params dict, hardcode default values, cleanup

This commit is contained in:
Eddie Hung 2019-08-28 10:06:40 -07:00
parent 64ea147236
commit c4d1bd988b
2 changed files with 21 additions and 25 deletions

29
passes/pmgen/xilinx_srl.cc
View File

@ -34,11 +34,6 @@ void run_fixed(xilinx_srl_pm &pm)
{ {
auto &st = pm.st_fixed; auto &st = pm.st_fixed;
auto &ud = pm.ud_fixed; auto &ud = pm.ud_fixed;
auto param_def = [&ud](Cell *cell, IdString param) {
auto def = ud.default_params.at(std::make_pair(cell->type,param));
return cell->parameters.at(param, def);
};
log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
auto first_cell = ud.longest_chain.back(); auto first_cell = ud.longest_chain.back();
@ -58,8 +53,12 @@ void run_fixed(xilinx_srl_pm &pm)
else else
initval.append(State::Sx); initval.append(State::Sx);
} }
else if (cell->type.in(ID(FDRE), ID(FDRE_1))) else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
initval.append(param_def(cell, ID(INIT))); if (cell->parameters.at(ID(INIT), State::S0).as_bool())
initval.append(State::S1);
else
initval.append(State::S0);
}
else else
log_abort(); log_abort();
if (cell != first_cell) if (cell != first_cell)
@ -77,8 +76,12 @@ void run_fixed(xilinx_srl_pm &pm)
c->setParam(ID(CLKPOL), 1); c->setParam(ID(CLKPOL), 1);
else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
c->setParam(ID(CLKPOL), 0); c->setParam(ID(CLKPOL), 0);
else if (first_cell->type.in(ID(FDRE))) else if (first_cell->type.in(ID(FDRE))) {
c->setParam(ID(CLKPOL), param_def(first_cell, ID(IS_C_INVERTED)).as_bool() ? 0 : 1); if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool())
c->setParam(ID(CLKPOL), 1);
else
c->setParam(ID(CLKPOL), 0);
}
else else
log_abort(); log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
@ -252,14 +255,8 @@ struct XilinxSrlPass : public Pass {
pm.ud_fixed.minlen = minlen; pm.ud_fixed.minlen = minlen;
pm.ud_variable.minlen = minlen; pm.ud_variable.minlen = minlen;
if (fixed) { if (fixed)
// TODO: How to get these automatically?
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0;
pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
pm.run_fixed(run_fixed); pm.run_fixed(run_fixed);
}
if (variable) if (variable)
pm.run_variable(run_variable); pm.run_variable(run_variable);
} }

17
passes/pmgen/xilinx_srl.pmg
View File

@ -4,7 +4,6 @@ state <IdString> clk_port en_port
udata <vector<Cell*>> chain longest_chain udata <vector<Cell*>> chain longest_chain
udata <pool<Cell*>> non_first_cells udata <pool<Cell*>> non_first_cells
udata <int> minlen udata <int> minlen
udata <dict<std::pair<IdString,IdString>,Const>> default_params
code code
non_first_cells.clear(); non_first_cells.clear();
@ -111,10 +110,10 @@ match next
index <SigBit> port(next, \Q) === port(first, \D) index <SigBit> port(next, \Q) === port(first, \D)
filter port(next, clk_port) == port(first, clk_port) filter port(next, clk_port) == port(first, clk_port)
filter en_port == IdString() || port(next, en_port) == port(first, en_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port)
filter !next->type.in(\FDRE) || !first->hasParam(\IS_C_INVERTED) || (next->hasParam(\IS_C_INVERTED) && param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()) filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool()
filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R)
endmatch endmatch
code code
@ -138,10 +137,10 @@ match next
index <SigBit> port(next, \Q) === port(chain.back(), \D) index <SigBit> port(next, \Q) === port(chain.back(), \D)
filter port(next, clk_port) == port(first, clk_port) filter port(next, clk_port) == port(first, clk_port)
filter en_port == IdString() || port(next, en_port) == port(first, en_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port)
filter !next->type.in(\FDRE) || !first->hasParam(\IS_C_INVERTED) || (next->hasParam(\IS_C_INVERTED) && param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()) filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool()
filter !next->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || (next->hasParam(\IS_D_INVERTED) && param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()) filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
filter !next->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || (next->hasParam(\IS_R_INVERTED) && param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()) filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
filter !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R) filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R)
generate generate
Cell *cell = module->addCell(NEW_ID, chain.back()->type); Cell *cell = module->addCell(NEW_ID, chain.back()->type);
cell->setPort(\C, chain.back()->getPort(\C)); cell->setPort(\C, chain.back()->getPort(\C));