mirror of https://github.com/YosysHQ/yosys.git
Merge Verific SVA preprocessor and SVA importer
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@ -1290,14 +1290,23 @@ VerificClockEdge::VerificClockEdge(VerificImporter *importer, Instance *inst)
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// ==================================================================
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// ==================================================================
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struct VerificSvaPP
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struct VerificSvaImporter
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{
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{
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VerificImporter *importer;
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Module *module;
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Netlist *netlist;
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Netlist *netlist;
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Instance *root;
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Instance *root;
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SigBit clock = State::Sx;
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bool clock_posedge = false;
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SigBit disable_iff = State::S0;
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bool mode_assert = false;
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bool mode_assert = false;
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bool mode_assume = false;
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bool mode_assume = false;
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bool mode_cover = false;
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bool mode_cover = false;
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bool eventually = false;
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bool did_something = false;
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bool did_something = false;
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Instance *net_to_ast_driver(Net *n)
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Instance *net_to_ast_driver(Net *n)
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@ -1329,6 +1338,9 @@ struct VerificSvaPP
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Instance *get_ast_input3(Instance *inst) { return net_to_ast_driver(inst->GetInput3()); }
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Instance *get_ast_input3(Instance *inst) { return net_to_ast_driver(inst->GetInput3()); }
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Instance *get_ast_control(Instance *inst) { return net_to_ast_driver(inst->GetControl()); }
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Instance *get_ast_control(Instance *inst) { return net_to_ast_driver(inst->GetControl()); }
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// ----------------------------------------------------------
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// SVA Preprocessor
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Net *rewrite_input(Instance *inst) { return rewrite(get_ast_input(inst), inst->GetInput()); }
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Net *rewrite_input(Instance *inst) { return rewrite(get_ast_input(inst), inst->GetInput()); }
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Net *rewrite_input1(Instance *inst) { return rewrite(get_ast_input1(inst), inst->GetInput1()); }
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Net *rewrite_input1(Instance *inst) { return rewrite(get_ast_input1(inst), inst->GetInput1()); }
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Net *rewrite_input2(Instance *inst) { return rewrite(get_ast_input2(inst), inst->GetInput2()); }
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Net *rewrite_input2(Instance *inst) { return rewrite(get_ast_input2(inst), inst->GetInput2()); }
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@ -1384,7 +1396,7 @@ struct VerificSvaPP
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return default_net;
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return default_net;
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}
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}
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void run()
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void rewrite()
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{
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{
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netlist = root->Owner();
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netlist = root->Owner();
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do {
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do {
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@ -1392,80 +1404,9 @@ struct VerificSvaPP
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rewrite(root);
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rewrite(root);
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} while (did_something);
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} while (did_something);
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}
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}
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};
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void svapp_assert(Instance *inst)
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// ----------------------------------------------------------
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{
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// SVA Inporter
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VerificSvaPP worker;
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worker.root = inst;
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worker.mode_assert = true;
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worker.run();
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}
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void svapp_assume(Instance *inst)
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{
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VerificSvaPP worker;
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worker.root = inst;
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worker.mode_assume = true;
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worker.run();
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}
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void svapp_cover(Instance *inst)
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{
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VerificSvaPP worker;
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worker.root = inst;
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worker.mode_cover = true;
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worker.run();
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}
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// ==================================================================
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struct VerificSvaImporter
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{
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VerificImporter *importer;
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Module *module;
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Netlist *netlist;
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Instance *root;
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SigBit clock = State::Sx;
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bool clock_posedge = false;
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SigBit disable_iff = State::S0;
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bool mode_assert = false;
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bool mode_assume = false;
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bool mode_cover = false;
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bool eventually = false;
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Instance *net_to_ast_driver(Net *n)
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{
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if (n == nullptr)
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return nullptr;
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if (n->IsMultipleDriven())
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return nullptr;
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Instance *inst = n->Driver();
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if (inst == nullptr)
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return nullptr;
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if (!verific_sva_prims.count(inst->Type()))
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return nullptr;
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if (inst->Type() == PRIM_SVA_ROSE || inst->Type() == PRIM_SVA_FELL ||
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inst->Type() == PRIM_SVA_STABLE || inst->Type() == OPER_SVA_STABLE || inst->Type() == PRIM_SVA_PAST)
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return nullptr;
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return inst;
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}
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Instance *get_ast_input(Instance *inst) { return net_to_ast_driver(inst->GetInput()); }
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Instance *get_ast_input1(Instance *inst) { return net_to_ast_driver(inst->GetInput1()); }
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Instance *get_ast_input2(Instance *inst) { return net_to_ast_driver(inst->GetInput2()); }
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Instance *get_ast_input3(Instance *inst) { return net_to_ast_driver(inst->GetInput3()); }
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Instance *get_ast_control(Instance *inst) { return net_to_ast_driver(inst->GetControl()); }
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struct sequence_t {
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struct sequence_t {
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int length = 0;
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int length = 0;
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@ -1568,7 +1509,7 @@ struct VerificSvaImporter
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log_warning("Unsupported Verific SVA primitive %s of type %s.\n", inst->Name(), inst->View()->Owner()->Name());
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log_warning("Unsupported Verific SVA primitive %s of type %s.\n", inst->Name(), inst->View()->Owner()->Name());
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}
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}
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void run()
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void import()
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{
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{
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module = importer->module;
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module = importer->module;
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netlist = root->Owner();
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netlist = root->Owner();
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@ -1651,13 +1592,37 @@ struct VerificSvaImporter
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}
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}
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};
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};
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void svapp_assert(Instance *inst)
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{
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VerificSvaImporter worker;
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worker.root = inst;
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worker.mode_assert = true;
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worker.rewrite();
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}
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void svapp_assume(Instance *inst)
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{
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VerificSvaImporter worker;
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worker.root = inst;
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worker.mode_assume = true;
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worker.rewrite();
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}
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void svapp_cover(Instance *inst)
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{
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VerificSvaImporter worker;
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worker.root = inst;
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worker.mode_cover = true;
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worker.rewrite();
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}
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void import_sva_assert(VerificImporter *importer, Instance *inst)
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void import_sva_assert(VerificImporter *importer, Instance *inst)
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{
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{
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VerificSvaImporter worker;
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VerificSvaImporter worker;
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worker.importer = importer;
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worker.importer = importer;
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worker.root = inst;
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worker.root = inst;
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worker.mode_assert = true;
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worker.mode_assert = true;
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worker.run();
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worker.import();
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}
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}
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void import_sva_assume(VerificImporter *importer, Instance *inst)
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void import_sva_assume(VerificImporter *importer, Instance *inst)
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@ -1666,7 +1631,7 @@ void import_sva_assume(VerificImporter *importer, Instance *inst)
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worker.importer = importer;
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worker.importer = importer;
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worker.root = inst;
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worker.root = inst;
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worker.mode_assume = true;
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worker.mode_assume = true;
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worker.run();
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worker.import();
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}
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}
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void import_sva_cover(VerificImporter *importer, Instance *inst)
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void import_sva_cover(VerificImporter *importer, Instance *inst)
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@ -1675,7 +1640,7 @@ void import_sva_cover(VerificImporter *importer, Instance *inst)
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worker.importer = importer;
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worker.importer = importer;
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worker.root = inst;
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worker.root = inst;
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worker.mode_cover = true;
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worker.mode_cover = true;
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worker.run();
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worker.import();
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}
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}
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// ==================================================================
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// ==================================================================
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