mirror of https://github.com/YosysHQ/yosys.git
Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
This commit is contained in:
parent
8f3d1f8fcf
commit
c3c2983d12
|
@ -19,6 +19,10 @@ module GP_ABUF(input wire IN, output wire OUT);
|
||||||
|
|
||||||
assign OUT = IN;
|
assign OUT = IN;
|
||||||
|
|
||||||
|
//must be 1, 5, 20, 50
|
||||||
|
//values >1 only available with Vdd > 2.7V
|
||||||
|
parameter BANDWIDTH_KHZ = 1;
|
||||||
|
|
||||||
//cannot simulate mixed signal IP
|
//cannot simulate mixed signal IP
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -412,6 +416,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
module GP_PWRDET(output reg VDD_LOW);
|
||||||
|
initial VDD_LOW = 0;
|
||||||
|
endmodule
|
||||||
|
|
||||||
module GP_POR(output reg RST_DONE);
|
module GP_POR(output reg RST_DONE);
|
||||||
parameter POR_TIME = 500;
|
parameter POR_TIME = 500;
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue