mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3280 from YosysHQ/micko/fix_readaiw
Fix reading aiw from other solvers
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commit
c3a3f68b4d
2
Makefile
2
Makefile
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@ -142,7 +142,7 @@ bumpversion:
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# is just a symlink to your actual ABC working directory, as 'make mrproper'
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# will remove the 'abc' directory and you do not want to accidentally
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# delete your work on ABC..
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ABCREV = 00b674d
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ABCREV = 3da9357
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ABCPULL = 1
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ABCURL ?= https://github.com/YosysHQ/abc
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ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 VERBOSE=$(Q)
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@ -1231,13 +1231,13 @@ struct SimWorker : SimShared
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{
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std::string line;
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std::getline(f, line);
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if (line.size()==0 || line[0]=='#') continue;
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if (line.size()==0 || line[0]=='#' || line[0]=='c' || line[0]=='f' || line[0]=='u') continue;
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if (line[0]=='.') break;
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if (state==0 && line.size()!=1) {
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// old format detected, latch data
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state = 2;
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}
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if (state==1 && line[0]!='b' && line[0]!='c') {
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if (state==1 && line[0]!='b' && line[0]!='j') {
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// was old format but with 1 bit latch
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top->setState(latches, status);
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state = 3;
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