mirror of https://github.com/YosysHQ/yosys.git
Force $inout.out ports to begin with '$' to indicate internal
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11ac37733d
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c340fbfab2
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@ -424,7 +424,7 @@ struct XAigerWriter
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// inherit existing inout's drivers
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// inherit existing inout's drivers
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if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
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if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
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|| keep_bits.count(bit)) {
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|| keep_bits.count(bit)) {
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RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
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RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
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RTLIL::Wire *new_wire = module->wire(wire_name);
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RTLIL::Wire *new_wire = module->wire(wire_name);
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if (!new_wire)
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if (!new_wire)
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new_wire = module->addWire(wire_name, GetSize(wire));
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new_wire = module->addWire(wire_name, GetSize(wire));
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@ -868,7 +868,7 @@ void AigerReader::post_process()
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if (!existing) {
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if (!existing) {
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if (escaped_s.ends_with("$inout.out")) {
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if (escaped_s.ends_with("$inout.out")) {
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wire->port_output = false;
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wire->port_output = false;
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RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
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RTLIL::Wire *in_wire = module->wire(escaped_s.substr(1, escaped_s.size()-11));
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log_assert(in_wire);
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log_assert(in_wire);
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log_assert(in_wire->port_input && !in_wire->port_output);
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log_assert(in_wire->port_input && !in_wire->port_output);
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in_wire->port_output = true;
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in_wire->port_output = true;
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@ -889,7 +889,7 @@ void AigerReader::post_process()
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if (!existing) {
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if (!existing) {
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if (escaped_s.ends_with("$inout.out")) {
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if (escaped_s.ends_with("$inout.out")) {
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wire->port_output = false;
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wire->port_output = false;
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RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
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RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(1, escaped_s.size()-11).c_str(), index));
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log_assert(in_wire);
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log_assert(in_wire);
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log_assert(in_wire->port_input && !in_wire->port_output);
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log_assert(in_wire->port_input && !in_wire->port_output);
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in_wire->port_output = true;
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in_wire->port_output = true;
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