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Disable RAM16X1D match rule; carry-over from LUT4 arches

This commit is contained in:
Eddie Hung 2019-12-13 08:59:17 -08:00
parent d6514fc2e1
commit c3262d6075
1 changed files with 9 additions and 6 deletions
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15
techlibs/xilinx/lutrams.txt
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@ -105,12 +105,15 @@ bram $__XILINX_RAM64M
endbram endbram
match $__XILINX_RAM16X1D # Disabled for now, pending support for LUT4 arches
min bits 2 # since on LUT6 arches this occupies same area as
min wports 1 # a RAM32X1D
make_outreg #match $__XILINX_RAM16X1D
or_next_if_better # min bits 2
endmatch # min wports 1
# make_outreg
# or_next_if_better
#endmatch
match $__XILINX_RAM32X1D match $__XILINX_RAM32X1D
min bits 3 min bits 3