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techmap: Fix cell names with _TECHMAP_REPLACE_.* 

Fixes #1804.
This commit is contained in:
Marcin Kościelnicki 2020-03-23 11:07:03 +01:00
parent beab15b77c
commit c2bf11e42a
2 changed files with 19 additions and 1 deletions
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2
passes/techmap/techmap.cc
View File

@ -177,10 +177,10 @@ struct TechmapWorker
std::string orig_cell_name; std::string orig_cell_name;
pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src)); pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
orig_cell_name = cell->name.str();
if (!flatten_mode) { if (!flatten_mode) {
for (auto &it : tpl->cells_) for (auto &it : tpl->cells_)
if (it.first == ID(_TECHMAP_REPLACE_)) { if (it.first == ID(_TECHMAP_REPLACE_)) {
orig_cell_name = cell->name.str();
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break; break;
} }

18
tests/techmap/techmap_replace.ys
View File

@ -16,3 +16,21 @@ EOT
techmap -map %techmap techmap -map %techmap
select -assert-any w:s0.asdf select -assert-any w:s0.asdf
select -assert-any c:s0.blah select -assert-any c:s0.blah
read_verilog <<EOT
module sub(input i, output o, input j);
wire _TECHMAP_REPLACE_.asdf = i ;
barfoo _TECHMAP_REPLACE_.blah (i, o, j);
endmodule
EOT
design -stash techmap
read_verilog <<EOT
module top(input i, output o);
sub s0(i, o);
endmodule
EOT
techmap -map %techmap
select -assert-any w:s0.asdf
select -assert-any c:s0.blah