From c244a7161b60e74a4db767016b45f4e5dec9920c Mon Sep 17 00:00:00 2001 From: Patrick Urban Date: Tue, 30 May 2023 09:05:43 +0200 Subject: [PATCH] gatemate: Fix SDP read behavior --- techlibs/gatemate/cells_sim.v | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index 12e01d2df..dbf2d514a 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -733,13 +733,12 @@ module CC_BRAM_20K ( // SDP read port always @(posedge clkb) begin - // "NO_CHANGE" only for (k=0; k < B_RD_WIDTH; k=k+1) begin if (k < 20) begin - if (enb && !wea) A_DO_out[k] <= memory[addrb+k]; + if (enb) A_DO_out[k] <= memory[addrb+k]; end else begin // use both ports - if (enb && !wea) B_DO_out[k-20] <= memory[addrb+k]; + if (enb) B_DO_out[k-20] <= memory[addrb+k]; end end end @@ -1274,13 +1273,12 @@ module CC_BRAM_40K ( // SDP read port always @(posedge clkb) begin - // "NO_CHANGE" only for (k=0; k < B_RD_WIDTH; k=k+1) begin if (k < 40) begin - if (enb && !wea) A_DO_out[k] <= memory[addrb+k]; + if (enb) A_DO_out[k] <= memory[addrb+k]; end else begin // use both ports - if (enb && !wea) B_DO_out[k-40] <= memory[addrb+k]; + if (enb) B_DO_out[k-40] <= memory[addrb+k]; end end end