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Regression testing for read-over-write emulation
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@ -6,6 +6,7 @@ chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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select -assert-none t:LUT4
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## With parameters
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@ -5,6 +5,9 @@ synth_gatemate -top sync_ram_sdp -noiopad
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cd sync_ram_sdp
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select -assert-count 1 t:CC_BUFG
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select -assert-count 1 t:CC_BRAM_20K
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select -assert-none t:CC_LUT3
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select -assert-none t:CC_LUT4
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select -assert-none t:CC_DFF
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# 512 x 80 bit -> CC_BRAM_40K SDP RAM
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design -reset
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@ -6,6 +6,8 @@ chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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select -assert-none t:SB_LUT4
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select -assert-none t:SB_DFF
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
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