riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add test

This commit is contained in:
Eddie Hung 2019-06-20 16:07:22 -07:00
parent c27ab609fa
commit c20adc5263
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
tests/simple/generate.v
View File

@ -148,3 +148,14 @@ generate
endgenerate endgenerate
assign out = steps[WIDTH].outer[0].val; assign out = steps[WIDTH].outer[0].val;
endmodule endmodule
// ------------------------------------------
module gen_test6(output [3:0] o);
generate
genvar i;
for (i = 3; i >= 0; i = i-1) begin
assign o[i] = 1'b0;
end
endgenerate
endmodule