diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 07f9ee45d..cc37677ce 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1411,6 +1411,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 			module->connect(conn);
 		}
 
+		cell_stats.sort();
 		for (auto &it : cell_stats)
 			log("ABC RESULTS:   %15s cells: %8d\n", it.first.c_str(), it.second);
 		int in_wires = 0, out_wires = 0;