riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cellmatch: Add debug print

This commit is contained in:
Martin Povišer 2024-04-13 16:56:44 +02:00 committed by Emil J. Tywoniak
parent 6a9858cdad
commit c0e68dcc4d
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/cellmatch.cc
View File

@ -185,6 +185,8 @@ struct CellmatchPass : Pass {
continue; continue;
for (auto lut : luts) for (auto lut : luts)
p_classes.insert(p_class(ninputs, lut)); p_classes.insert(p_class(ninputs, lut));
log_debug("Registered %s\n", log_id(m));
// save as a viable target // save as a viable target
targets[p_classes].push_back(Target{m, luts}); targets[p_classes].push_back(Target{m, luts});